zero-pad sized integrals no larger than 256 bits

ddaa7ff6 · Zachary Snow · 50a6966a · ddaa7ff6
Commit ddaa7ff6 authored Aug 09, 2020 by Zachary Snow
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src/Language/SystemVerilog/AST/Number.hs
+1 -1

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--- a/src/Language/SystemVerilog/AST/Number.hs
+++ b/src/Language/SystemVerilog/AST/Number.hs
@@ -237,7 +237,7 @@ showBasedDigits base size values kinds =
        padList '0' sizeDigits digits
    else if leadingXZ && size < 0 then
        removeExtraPadding digits
-    else if leadingXZ || (32 > size && size > 0) then
+    else if leadingXZ || (256 >= size && size > 0) then
        padList '0' sizeDigits digits
    else
        digits