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lvzhengyang
sv2v
Commits
da38776d
Commit
da38776d
authored
Apr 23, 2019
by
Zachary Snow
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decls are now package items
parent
d01df611
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Showing
8 changed files
with
51 additions
and
42 deletions
+51
-42
src/Convert/Enum.hs
+1
-1
src/Convert/Interface.hs
+10
-9
src/Convert/Logic.hs
+4
-4
src/Convert/Traverse.hs
+12
-11
src/Language/SystemVerilog/AST/Description.hs
+3
-1
src/Language/SystemVerilog/AST/ModuleItem.hs
+1
-3
src/Language/SystemVerilog/Parser/Parse.y
+18
-11
src/Language/SystemVerilog/Parser/ParseDecl.hs
+2
-2
No files found.
src/Convert/Enum.hs
View file @
da38776d
...
...
@@ -73,7 +73,7 @@ convergeUsage items enums =
toItem
::
EnumItem
->
ModuleItem
toItem
((
r
,
x
),
v
)
=
MIDecl
$
Localparam
itemType
x
v'
MI
PackageItem
$
Decl
$
Localparam
itemType
x
v'
where
v'
=
sizedExpr
x
r
(
simplify
v
)
itemType
=
Implicit
Unspecified
[
r
]
...
...
src/Convert/Interface.hs
View file @
da38776d
...
...
@@ -58,7 +58,7 @@ convertDescription interfaces modules (Part extern Module lifetime name ports it
(
instances
,
modports
)
=
execWriter
$
mapM
(
collectNestedModuleItemsM
collectInterface
)
items
collectInterface
::
ModuleItem
->
Writer
(
Instances
,
Modports
)
()
collectInterface
(
MI
Decl
(
Variable
_
t
ident
_
_
))
=
collectInterface
(
MI
PackageItem
(
Decl
(
Variable
_
t
ident
_
_
)
))
=
case
t
of
InterfaceT
interfaceName
(
Just
modportName
)
[]
->
tell
(
Map
.
empty
,
Map
.
singleton
ident
modportDecls
)
...
...
@@ -71,10 +71,11 @@ convertDescription interfaces modules (Part extern Module lifetime name ports it
collectInterface
_
=
return
()
mapInterface
::
ModuleItem
->
ModuleItem
mapInterface
(
orig
@
(
MI
Decl
(
Variable
Local
t
ident
_
_
)))
=
mapInterface
(
orig
@
(
MI
PackageItem
(
Decl
(
Variable
Local
t
ident
_
_
)
)))
=
case
Map
.
lookup
ident
modports
of
Just
modportDecls
->
Generate
$
map
(
GenModuleItem
.
MIDecl
.
mapper
)
modportDecls
map
(
GenModuleItem
.
MIPackageItem
.
Decl
.
mapper
)
modportDecls
Nothing
->
orig
where
InterfaceT
interfaceName
(
Just
_
)
[]
=
t
...
...
@@ -208,7 +209,7 @@ lookupType items (Ident ident) =
ts
->
head
ts
where
findType
::
ModuleItem
->
Maybe
(
Type
,
[
Range
])
findType
(
MI
Decl
(
Variable
_
t
x
rs
Nothing
))
=
findType
(
MI
PackageItem
(
Decl
(
Variable
_
t
x
rs
Nothing
)
))
=
if
x
==
ident
then
Just
(
t
,
rs
)
else
Nothing
findType
_
=
Nothing
lookupType
_
expr
=
...
...
@@ -222,7 +223,7 @@ inlineInterface (ports, items) (instanceName, instancePorts) =
(
:
)
(
MIPackageItem
$
Comment
$
"expanded instance: "
++
instanceName
)
$
flip
(
++
)
portBindings
$
map
(
traverseNestedModuleItems
removeModport
)
$
map
(
traverseNestedModuleItems
remove
MI
DeclDir
)
$
map
(
traverseNestedModuleItems
removeDeclDir
)
$
itemsPrefixed
where
prefix
=
instanceName
++
"_"
...
...
@@ -238,10 +239,10 @@ inlineInterface (ports, items) (instanceName, instancePorts) =
mapMaybe
portBindingItem
$
zip
instancePortNames
instancePortExprs
remove
MI
DeclDir
::
ModuleItem
->
ModuleItem
remove
MIDeclDir
(
MIDecl
(
Variable
_
t
x
a
me
))
=
MIDecl
$
Variable
Local
t
x
a
me
remove
MI
DeclDir
other
=
other
removeDeclDir
::
ModuleItem
->
ModuleItem
remove
DeclDir
(
MIPackageItem
(
Decl
(
Variable
_
t
x
a
me
)
))
=
MI
PackageItem
$
Decl
$
Variable
Local
t
x
a
me
removeDeclDir
other
=
other
removeModport
::
ModuleItem
->
ModuleItem
removeModport
(
Modport
x
_
)
=
MIPackageItem
$
Comment
$
"removed modport "
++
x
...
...
src/Convert/Logic.hs
View file @
da38776d
...
...
@@ -43,7 +43,7 @@ convert ast =
collectModuleItemsM
collectPortDirsM
orig
where
collectPortDirsM
::
ModuleItem
->
Writer
Ports
()
collectPortDirsM
(
MI
Decl
(
Variable
dir
_
ident
_
_
))
=
collectPortDirsM
(
MI
PackageItem
(
Decl
(
Variable
dir
_
ident
_
_
)
))
=
if
dir
==
Local
then
return
()
else
if
elem
ident
portNames
then
...
...
@@ -100,7 +100,7 @@ convertDescription ports orig =
tmpExpr
=
Ident
tmp
t
=
Net
TWire
[(
Bits
$
Right
expr
,
Number
"1"
)]
items
=
[
MIDecl
$
Variable
Local
t
tmp
[]
Nothing
[
MI
PackageItem
$
Decl
$
Variable
Local
t
tmp
[]
Nothing
,
AlwaysC
AlwaysComb
$
AsgnBlk
AsgnOpEq
lhs
tmpExpr
]
lhs
=
case
exprToLHS
expr
of
Just
l
->
l
...
...
@@ -110,8 +110,8 @@ convertDescription ports orig =
++
portName
++
" of "
++
instanceName
fixBinding
other
=
(
other
,
[]
)
-- rewrite variable declarations to have the correct type
convertModuleItem
(
MI
Decl
(
Variable
dir
(
IntegerVector
TLogic
sg
mr
)
ident
a
me
))
=
MIDecl
$
Variable
dir
(
t
mr
)
ident
a
me
convertModuleItem
(
MI
PackageItem
(
Decl
(
Variable
dir
(
IntegerVector
TLogic
sg
mr
)
ident
a
me
)
))
=
MI
PackageItem
$
Decl
$
Variable
dir
(
t
mr
)
ident
a
me
where
t
=
if
sg
/=
Unspecified
||
Set
.
member
ident
idents
then
IntegerVector
TReg
sg
...
...
src/Convert/Traverse.hs
View file @
da38776d
...
...
@@ -151,14 +151,15 @@ traverseModuleItemsM mapper (PackageItem packageItem) = do
return
$
case
item'
of
MIPackageItem
packageItem'
->
PackageItem
packageItem'
other
->
error
$
"encountered bad package module item: "
++
show
other
traverseModuleItemsM
mapper
(
Package
lifetime
name
items
)
=
do
traverseModuleItemsM
mapper
(
Package
lifetime
name
packageItems
)
=
do
let
items
=
map
MIPackageItem
packageItems
converted
<-
traverseModuleItemsM
mapper
(
Part
False
Module
Nothing
"DNE"
[]
items
)
let
items'
=
case
converted
of
Part
False
Module
Nothing
"DNE"
[]
newItems
->
newItems
_
->
error
$
"redirected Package traverse failed: "
++
show
converted
return
$
Package
lifetime
name
items'
return
$
Package
lifetime
name
$
map
(
\
(
MIPackageItem
item
)
->
item
)
items'
traverseModuleItemsM
_
(
Directive
str
)
=
return
$
Directive
str
traverseModuleItems
::
Mapper
ModuleItem
->
Mapper
Description
...
...
@@ -503,8 +504,8 @@ traverseExprsM' strat exprMapper = moduleItemMapper
moduleItemMapper
(
MIAttr
attr
mi
)
=
-- note: we exclude expressions in attributes from conversion
return
$
MIAttr
attr
mi
moduleItemMapper
(
MI
Decl
decl
)
=
declMapper
decl
>>=
return
.
MIDecl
moduleItemMapper
(
MI
PackageItem
(
Decl
decl
)
)
=
declMapper
decl
>>=
return
.
MI
PackageItem
.
Decl
moduleItemMapper
(
Defparam
lhs
expr
)
=
do
lhs'
<-
lhsMapper
lhs
expr'
<-
exprMapper
expr
...
...
@@ -725,8 +726,8 @@ traverseDeclsM' strat mapper item = do
item'
<-
miMapper
item
traverseStmtsM'
strat
stmtMapper
item'
where
miMapper
(
MI
Decl
decl
)
=
mapper
decl
>>=
return
.
MIDecl
miMapper
(
MI
PackageItem
(
Decl
decl
)
)
=
mapper
decl
>>=
return
.
MI
PackageItem
.
Decl
miMapper
(
MIPackageItem
(
Function
l
t
x
decls
stmts
))
=
do
decls'
<-
if
strat
==
IncludeTFs
...
...
@@ -921,7 +922,7 @@ collectNestedExprsM = collectify traverseNestedExprsM
-- Traverse all the declaration scopes within a ModuleItem. Note that Functions,
-- Tasks, Always and Initial blocks are all NOT passed through ModuleItem
-- mapper, and
MI
Decl ModuleItems are NOT passed through the Decl mapper. The
-- mapper, and Decl ModuleItems are NOT passed through the Decl mapper. The
-- state is restored to its previous value after each scope is exited. Only the
-- Decl mapper may modify the state, as we maintain the invariant that all other
-- functions restore the state on exit. The Stmt mapper must not traverse
...
...
@@ -992,12 +993,12 @@ scopedConversion
scopedConversion
traverseDeclM
traverseModuleItemM
traverseStmtM
s
description
=
evalState
(
initialTraverse
description
>>=
scopedTraverse
)
s
where
initialTraverse
=
traverseModuleItemsM
traverseMIDecl
initialTraverse
=
traverseModuleItemsM
traverseMI
PackageItem
Decl
scopedTraverse
=
traverseModuleItemsM
$
traverseScopesM
traverseDeclM
traverseModuleItemM
traverseStmtM
traverseMI
Decl
(
MIDecl
decl
)
=
traverseDeclM
decl
>>=
return
.
MIDecl
traverseMIDecl
other
=
return
other
traverseMI
PackageItemDecl
(
MIPackageItem
(
Decl
decl
)
)
=
traverseDeclM
decl
>>=
return
.
MI
PackageItem
.
Decl
traverseMI
PackageItem
Decl
other
=
return
other
-- convert a basic mapper with an initial argument to a stateful mapper
stately
::
(
Eq
s
,
Show
s
)
=>
(
s
->
Mapper
a
)
->
MapperM
(
State
s
)
a
...
...
src/Language/SystemVerilog/AST/Description.hs
View file @
da38776d
...
...
@@ -26,7 +26,7 @@ import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
data
Description
=
Part
Bool
PartKW
(
Maybe
Lifetime
)
Identifier
[
Identifier
]
[
ModuleItem
]
|
PackageItem
PackageItem
|
Package
(
Maybe
Lifetime
)
Identifier
[
Modul
eItem
]
|
Package
(
Maybe
Lifetime
)
Identifier
[
Packag
eItem
]
|
Directive
String
-- currently unused
deriving
Eq
...
...
@@ -57,6 +57,7 @@ data PackageItem
|
Function
(
Maybe
Lifetime
)
Type
Identifier
[
Decl
]
[
Stmt
]
|
Task
(
Maybe
Lifetime
)
Identifier
[
Decl
]
[
Stmt
]
|
Import
[(
Identifier
,
Maybe
Identifier
)]
|
Decl
Decl
|
Comment
String
deriving
Eq
...
...
@@ -75,6 +76,7 @@ instance Show PackageItem where
(
commas
$
map
showImport
imports
)
where
showImport
(
x
,
y
)
=
printf
"%s::%s"
x
(
fromMaybe
"*"
y
)
show
(
Decl
decl
)
=
show
decl
show
(
Comment
c
)
=
if
elem
'
\n
'
c
then
"// "
++
show
c
...
...
src/Language/SystemVerilog/AST/ModuleItem.hs
View file @
da38776d
...
...
@@ -21,7 +21,7 @@ import Text.Printf (printf)
import
Language.SystemVerilog.AST.ShowHelp
import
Language.SystemVerilog.AST.Attr
(
Attr
)
import
Language.SystemVerilog.AST.Decl
(
D
ecl
,
D
irection
)
import
Language.SystemVerilog.AST.Decl
(
Direction
)
import
Language.SystemVerilog.AST.Description
(
PackageItem
)
import
Language.SystemVerilog.AST.Expr
(
Expr
(
Ident
),
Range
,
showRanges
)
import
Language.SystemVerilog.AST.GenItem
(
GenItem
)
...
...
@@ -31,7 +31,6 @@ import Language.SystemVerilog.AST.Type (Identifier)
data
ModuleItem
=
MIAttr
Attr
ModuleItem
|
MIDecl
Decl
|
AlwaysC
AlwaysKW
Stmt
|
Assign
(
Maybe
Expr
)
LHS
Expr
|
Defparam
LHS
Expr
...
...
@@ -47,7 +46,6 @@ data ModuleItem
deriving
Eq
instance
Show
ModuleItem
where
show
(
MIDecl
nest
)
=
show
nest
show
(
MIPackageItem
i
)
=
show
i
show
(
MIAttr
attr
mi
)
=
printf
"%s %s"
(
show
attr
)
(
show
mi
)
show
(
AlwaysC
k
b
)
=
printf
"%s %s"
(
show
k
)
(
show
b
)
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
da38776d
...
...
@@ -256,13 +256,13 @@ opt(p) :: { Maybe a }
Descriptions :: { [Description] }
: {- empty -} { [] }
| Descriptions ";" { $1 }
| Descriptions Description { $1 ++
[$2]
}
| Descriptions Description { $1 ++
$2
}
Description :: {
Description
}
: Part(ModuleKW , "endmodule" ) {
$1
}
| Part(InterfaceKW, "endinterface") {
$1
}
| Package
Item { PackageItem $1
}
| Package
Declaration {
$1 }
Description :: {
[Description]
}
: Part(ModuleKW , "endmodule" ) {
[$1]
}
| Part(InterfaceKW, "endinterface") {
[$1]
}
| Package
Declaration { [$1]
}
| Package
Item { map PackageItem
$1 }
Type :: { Type }
: TypeNonIdent { $1 }
...
...
@@ -344,7 +344,7 @@ InterfaceKW :: { PartKW }
: "interface" { Interface }
PackageDeclaration :: { Description }
: "package" opt(Lifetime) Identifier ";"
Modul
eItems "endpackage" opt(Tag) { Package $2 $3 $5 }
: "package" opt(Lifetime) Identifier ";"
Packag
eItems "endpackage" opt(Tag) { Package $2 $3 $5 }
Tag :: { Identifier }
: ":" Identifier { $2 }
...
...
@@ -356,7 +356,7 @@ ParamDecls :: { [ModuleItem] }
: ParamDecl(")") { $1 }
| ParamDecl(",") ParamDecls { $1 ++ $2 }
ParamDecl(delim) :: { [ModuleItem] }
: ParameterDecl(OnlyParamKW, delim) { map
MIDecl
$1 }
: ParameterDecl(OnlyParamKW, delim) { map
(MIPackageItem . Decl)
$1 }
OnlyParamKW :: { Type -> Identifier -> Expr -> Decl }
: "parameter" { Parameter }
...
...
@@ -447,14 +447,14 @@ ModuleItem :: { [ModuleItem] }
NonGenerateModuleItem :: { [ModuleItem] }
-- This item covers module instantiations and all declarations
: DeclTokens(";") { parseDTsAsModuleItems $1 }
| ParameterDecl(ParameterDeclKW, ";") { map
MIDecl
$1 }
| ParameterDecl(ParameterDeclKW, ";") { map
(MIPackageItem . Decl)
$1 }
| "defparam" DefparamAsgns ";" { map (uncurry Defparam) $2 }
| "assign" opt(DelayControl) LHS "=" Expr ";" { [Assign $2 $3 $5] }
| AlwaysKW Stmt { [AlwaysC $1 $2] }
| "initial" Stmt { [Initial $2] }
| "genvar" Identifiers ";" { map Genvar $2 }
| "modport" ModportItems ";" { map (uncurry Modport) $2 }
|
PackageItem
{ [MIPackageItem $1] }
|
NonDeclPackageItem
{ [MIPackageItem $1] }
| NInputGateKW NInputGates ";" { map (\(a, b, c) -> NInputGate $1 a b c) $2 }
| NOutputGateKW NOutputGates ";" { map (\(a, b, c) -> NOutputGate $1 a b c) $2 }
| AttributeInstance ModuleItem { map (MIAttr $1) $2 }
...
...
@@ -564,7 +564,14 @@ DefparamAsgns :: { [(LHS, Expr)] }
DefparamAsgn :: { (LHS, Expr) }
: LHS "=" Expr { ($1, $3) }
PackageItem :: { PackageItem }
PackageItems :: { [PackageItem] }
: PackageItem { $1 }
| PackageItems PackageItem { $1 ++ $2 }
PackageItem :: { [PackageItem] }
: DeclTokens(";") { map Decl $ parseDTsAsDecls $1 }
| ParameterDecl(ParameterDeclKW, ";") { map Decl $1 }
| NonDeclPackageItem { [$1] }
NonDeclPackageItem :: { PackageItem }
: "typedef" Type Identifier ";" { Typedef $2 $3 }
| "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5) }
| "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5) }
...
...
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
da38776d
...
...
@@ -84,7 +84,7 @@ parseDTsAsPortDecls pieces =
forbidNonEqAsgn
pieces
$
if
isSimpleList
then
(
simpleIdents
,
[]
)
else
(
portNames
declarations
,
map
MIDecl
declarations
)
else
(
portNames
declarations
,
map
(
MIPackageItem
.
Decl
)
declarations
)
where
commaIdxs
=
findIndices
isComma
pieces
identIdxs
=
findIndices
isIdent
pieces
...
...
@@ -116,7 +116,7 @@ parseDTsAsModuleItems tokens =
forbidNonEqAsgn
tokens
$
if
any
isInstance
tokens
then
parseDTsAsIntantiations
tokens
else
map
MIDecl
$
parseDTsAsDecl
tokens
else
map
(
MIPackageItem
.
Decl
)
$
parseDTsAsDecl
tokens
where
isInstance
::
DeclToken
->
Bool
isInstance
(
DTInstance
_
)
=
True
...
...
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