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Commit d95a5628 by Zachary Snow
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split out basic suite tests with refs to new core suite

parent bb938f1e
Showing with 3341 additions and 3339 deletions
test/basic/package_enum_1.v deleted 100644 → 0
module top;
wire [2:0] test;
assign test = 3'd0;
initial $display(test);
endmodule
test/basic/package_enum_3.sv deleted 100644 → 0
package foo_pkg;
typedef enum logic [2:0] {
AccessAck = 3'd0,
AccessAckData = 3'd1
} inp_t;
endpackage
module top;
import foo_pkg::*;
wire [2:0] test;
always_comb begin
case (test)
AccessAck: $display("Ack");
default : $display("default");
endcase
end
endmodule
test/basic/package_export_wildcard.sv deleted 100644 → 0
package P;
localparam X = 1;
endpackage
package Q;
import P::X;
export P::*;
localparam Y = 2;
endpackage
package R;
import Q::X;
export Q::*;
localparam Z = 3;
endpackage
package S;
import P::X;
import Q::Y;
import R::Z;
export *::*;
endpackage
module top;
import S::*;
initial $display(X, Y, Z);
endmodule
test/basic/package_function_cast.sv deleted 100644 → 0
package P;
function automatic logic [7:0] f(input logic [2:0] p);
logic [7:0] r;
localparam T = $bits(r[7:0]);
r = T'(1'sb0);
r[p+:2] = $bits(r[p+:2])'(1'sb1);
return r;
endfunction
endpackage
module top;
logic [2:0] p;
logic [7:0] q;
assign q = P::f(p);
initial begin
$monitor("%0d, p=%b q=%b", $time, p, q);
#1 p = 0;
while (p != 7)
#1 p = p + 1;
end
endmodule
test/basic/package_function_cast.v deleted 100644 → 0
module top;
function automatic [7:0] f;
input [2:0] p;
begin
f = 7'b0;
f[p+:2] = 2'b11;
end
endfunction
reg [2:0] p;
wire [7:0] q;
assign q = f(p);
initial begin
$monitor("%0d, p=%b q=%b", $time, p, q);
#1 p = 0;
while (p != 7)
#1 p = p + 1;
end
endmodule
test/basic/package_global.sv deleted 100644 → 0
package PkgA;
localparam X = 1;
localparam Y = 2;
endpackage
package PkgB;
localparam X = 3;
localparam Z = 4;
endpackage
import PkgA::*;
import PkgB::*;
localparam X = 5;
module top;
initial $display(X, Y, Z);
endmodule
test/basic/package_global.v deleted 100644 → 0
module top;
localparam X = 5;
localparam Y = 2;
localparam Z = 4;
initial $display(X, Y, Z);
endmodule
test/basic/package_implied.v deleted 100644 → 0
module top;
localparam P_X = 10;
localparam Y = P_X;
initial $display(Y);
endmodule
test/basic/package_order.sv deleted 100644 → 0
package evil_pkg;
localparam Z = 1;
localparam A = Z;
localparam B = Z;
function logic evil_fun;
return A;
endfunction
endpackage
module evil_mdl (
output logic [evil_pkg::B-1:0] foo
);
initial foo = evil_pkg::evil_fun();
endmodule
module top;
logic [evil_pkg::B-1:0] foo;
evil_mdl x(foo);
initial $monitor(foo);
endmodule
test/basic/package_order.v deleted 100644 → 0
module evil_mdl (
output reg [evil_pkg_B-1:0] foo
);
localparam evil_pkg_Z = 1;
localparam evil_pkg_A = evil_pkg_Z;
localparam evil_pkg_B = evil_pkg_Z;
initial foo = evil_pkg_A;
endmodule
module top;
localparam evil_pkg_Z = 1;
localparam evil_pkg_A = evil_pkg_Z;
localparam evil_pkg_B = evil_pkg_Z;
wire [evil_pkg_B-1:0] foo;
evil_mdl x(foo);
initial $monitor(foo);
endmodule
test/basic/package_param_tb.v deleted 100644 → 0
module top;
Example e1();
Example #(8) e2();
Example #(9) e3();
endmodule
test/basic/package_pattern.sv deleted 100644 → 0
package PKG;
typedef struct packed {
logic f;
} foo_t;
endpackage
module top;
typedef struct packed {
PKG::foo_t f;
} local_t;
local_t w[0:1];
initial begin
w <= '{default: 0};
$display("%b", w);
end
endmodule
test/basic/package_scope.v deleted 100644 → 0
module top;
initial begin
$display("A 3");
$display("B 3");
$display("C 1");
$display("D 2");
$display("E 2");
$display("F 2");
// G doesn't print
$display("H 1");
$display("I 1");
$display("J 1");
$display("K1 1");
$display("K2 2");
$display("K3 3");
$display("K4 2");
$display("K0 1");
$display("L 1");
$display("M1 1");
$display("M2 1");
$display("M3 1");
$display("M4 1");
$display("W::help() 1");
$display("W::help() 1");
$display("N1 1");
$display("N2 2");
$display("O1 1");
$display("O2 2");
end
endmodule
test/basic/package_self_reference.v deleted 100644 → 0
module top;
localparam Foo = 1;
initial $display(Foo);
endmodule
test/basic/package_self_reference_import.v deleted 100644 → 0
module top;
localparam Foo = 1;
initial $display(Foo);
endmodule
test/basic/package_self_reference_shadow.sv deleted 100644 → 0
package P;
localparam Bar = 1;
function automatic integer func;
localparam Bar = 2;
func = Bar + P::Bar;
endfunction
endpackage
module top;
import P::*;
initial $display(func());
endmodule
test/basic/package_self_reference_shadow.v deleted 100644 → 0
module top;
localparam Foo = 1;
localparam Bar = 2;
initial $display(Foo + Bar);
endmodule
test/basic/package_shadow.sv deleted 100644 → 0
package P;
localparam X = 10;
localparam Y = X + 1;
function integer flip;
input integer X;
return ~X;
endfunction
endpackage
package Q;
import P::*;
localparam Y = X + 1000;
endpackage
package R;
import Q::*;
export Q::Y;
endpackage
package S;
typedef enum logic { A, B } enum_t;
function enum_t flop;
input enum_t X;
if (X == A) return B;
else return A;
endfunction
endpackage
module top;
import P::*;
localparam X = 20;
localparam Z = Y + 1;
import S::flop;
typedef enum logic [3:0] { T = 3, U } enum_t;
initial begin
$display("X %0d", X);
$display("P::Y %0d", P::Y);
$display("Z %0d", Z);
$display("R::Y %0d", R::Y);
$display("flip(0) %0d", flip(0));
$display("T %b", T);
$display("U %b", U);
$display("flop(0) %b", flop(0));
$display("flop(1) %b", flop(1));
end
endmodule
test/basic/package_shadow.v deleted 100644 → 0
module top;
localparam P_X = 10;
localparam P_Y = P_X + 1;
localparam X = 20;
localparam Z = P_Y + 1;
localparam R_Y = P_X + 1000;
localparam Q_Y = R_Y;
localparam [3:0] T = 3;
localparam [3:0] U = 4;
function integer flip;
input integer inp;
flip = ~inp;
endfunction
function flop;
input inp;
flop = ~inp;
endfunction
initial begin
$display("X %0d", X);
$display("P::Y %0d", P_Y);
$display("Z %0d", Z);
$display("R::Y %0d", Q_Y);
$display("flip(0) %0d", flip(0));
$display("T %b", T);
$display("U %b", U);
$display("flop(0) %b", flop(0));
$display("flop(1) %b", flop(1));
end
endmodule
test/basic/package_typedef.sv deleted 100644 → 0
package top_pkg;
localparam AW = 16;
endpackage
package foo_pkg;
typedef struct packed {
logic valid;
logic value;
} mask_t;
typedef struct packed {
logic valid;
logic [top_pkg::AW-1:0] user;
mask_t mask;
} boo_t;
endpackage
module top;
foo_pkg::boo_t foo;
assign foo = 19'b110_01001000_01110100;
wire [7:0] bar;
parameter FLAG = 1;
assign bar = FLAG ? foo.user[0+:8] : '1;
endmodule
test/basic/package_typedef.v deleted 100644 → 0
module top;
localparam AW = 16;
wire [AW+2:0] foo;
assign foo = 19'b110_01001000_01110100;
wire [7:0] bar;
parameter FLAG = 1;
assign bar = FLAG ? foo[2+:8] : 8'hFF;
endmodule
test/basic/package_typedef_nested.sv deleted 100644 → 0
package foo_pkg;
typedef struct packed {
logic [7:0] rsvd;
logic [7:0] parity;
} user_t;
typedef struct packed {
logic valid;
user_t user;
} inp_t;
typedef struct packed {
logic valid;
logic opcode;
} out_t;
endpackage
module top (
input foo_pkg::inp_t dat_i,
output foo_pkg::out_t dat_o
);
endmodule
test/basic/package_typedef_nested.v deleted 100644 → 0
module top (dat_i, dat_o);
input wire [16:0] dat_i;
output wire [1:0] dat_o;
endmodule
test/basic/packed_array.sv deleted 100644 → 0
module top;
logic [2:0][3:0] arr [1:0];
initial begin
for (int i = 0; i <= 1; i++) begin
for (int j = 0; j <= 2; j++) begin
for (int k = 0; k <= 3; k++) begin
$display("%b", arr[i][j][k]);
arr[i][j][k] = 1'(i+j+k);
$display("%b", arr[i][j][k]);
end
end
end
end
endmodule
test/basic/packed_array.v deleted 100644 → 0
module top;
reg arr [1:0][2:0][3:0];
initial begin : block_name
integer i, j, k;
for (i = 0; i <= 1; i++) begin
for (j = 0; j <= 2; j++) begin
for (k = 0; k <= 3; k++) begin
$display("%b", arr[i][j][k]);
arr[i][j][k] = i+j+k;
$display("%b", arr[i][j][k]);
end
end
end
end
endmodule
test/basic/param_shorthand.sv deleted 100644 → 0
module top #(FOO = 10);
initial $display(FOO);
endmodule
module top2 #(FOO = 10, BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(FOO = 10, BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule
test/basic/param_shorthand.v deleted 100644 → 0
module top #(parameter FOO = 10);
initial $display(FOO);
endmodule
module top2 #(parameter FOO = 10, parameter BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(parameter FOO = 10, parameter BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule
test/basic/parameterized_data_types.sv deleted 100644 → 0
class P #(
parameter WIDTH = 1,
parameter type BASE = logic
);
typedef BASE [WIDTH - 1:0] Unit;
endclass
`define DUMP \
begin \
a = '1; \
b = '1; \
c = '1; \
d = '1; \
e = '1; \
$display("%b %b %b %b %b", a, b, c, d, e); \
end
module top;
localparam X = 2;
localparam type T = logic [31:0];
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
initial `DUMP
if (1) begin : blk
localparam X = 3;
localparam type T = logic [7:0];
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
initial `DUMP
end
if (1) begin : route
localparam X = 3;
localparam type T = logic [7:0];
initial begin
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
end
end
endmodule
test/basic/parameterized_data_types.v deleted 100644 → 0
`define DUMP \
begin \
a = 1'sb1; \
b = 1'sb1; \
c = 1'sb1; \
d = 1'sb1; \
e = 1'sb1; \
$display("%b %b %b %b %b", a, b, c, d, e); \
end
module top;
reg [0:0] a;
reg [1:0] b;
reg [63:0] c;
reg [1:0] d;
reg [31:0] e;
initial `DUMP
generate
if (1) begin : blk
reg [0:0] a;
reg [2:0] b;
reg [23:0] c;
reg [2:0] d;
reg [7:0] e;
initial
repeat (4)
`DUMP
end
endgenerate
endmodule
test/basic/paramtype_bits.sv deleted 100644 → 0
module Module(out);
parameter type T = logic;
output T out;
assign out = '1;
endmodule
module top;
logic w;
logic [$bits(w)-1:0] b;
logic o0, o1;
logic [1:0] o2;
Module m0(o0);
Module #(logic[$bits(w)-1:0]) m1(o1);
Module #(logic[$bits(b)*2-1:0]) m2(o2);
endmodule
test/basic/paramtype_bits.v deleted 100644 → 0
module Module_Size1(out);
output wire out;
assign out = 1'b1;
endmodule
module Module_Size2(out);
output wire [1:0] out;
assign out = 2'b11;
endmodule
module top;
wire w;
wire [0:0] b;
wire o0, o1;
wire [1:0] o2;
Module_Size1 m0(o0);
Module_Size1 m1(o1);
Module_Size2 m2(o2);
endmodule
test/basic/paramtype_delay.sv deleted 100644 → 0
module mod #(
parameter STR = "",
parameter type T = logic,
parameter WIDTH = 32,
parameter type WIDTH_T = logic [WIDTH-1:0],
parameter T INDIRECT = 0,
parameter type OTHER_T = struct packed { type(INDIRECT) x, y; }
);
initial begin
$display("%s $bits(T) = %0d", STR, $bits(T));
$display("%s WIDTH = %0d", STR, WIDTH);
$display("%s $bits(WIDTH_T) = %0d", STR, $bits(WIDTH_T));
$display("%s $bits(OTHER_T) = %0d", STR, $bits(OTHER_T));
end
endmodule
module top;
parameter type BASE = byte;
typedef struct packed { BASE y; } W;
W w;
typedef struct packed { type(w) x, y; } V;
V v;
typedef logic [$bits(v)*2-1:0] U;
U u;
`define TEST(x) \
assign x = 0; \
mod #(`"x`", type(x)) m``x();
`TEST(w)
`TEST(v)
`TEST(u)
mod #("t") mt();
endmodule
test/basic/paramtype_delay.v deleted 100644 → 0
module mod #(
parameter STR = "",
parameter T = 1
);
initial begin
$display("%s $bits(T) = %0d", STR, T);
$display("%s WIDTH = %0d", STR, 32);
$display("%s $bits(WIDTH_T) = %0d", STR, 32);
$display("%s $bits(OTHER_T) = %0d", STR, 2 * T);
end
endmodule
module top;
`define TEST(x, w) \
wire [w-1:0] x; \
assign x = 0; \
mod #(`"x`", w) m``x();
`TEST(w, 8)
`TEST(v, 16)
`TEST(u, 32)
mod #("t") mt();
endmodule
test/basic/paramtype_expr.sv deleted 100644 → 0
module mod #(
parameter type T = logic
);
initial $display("$bits(T) = %0d", $bits(T));
endmodule
module top;
parameter SIZE = 8;
mod #(logic [SIZE-1:0]) m();
endmodule
test/basic/paramtype_expr.v deleted 100644 → 0
module mod #(
parameter S = 1
);
initial $display("$bits(T) = %0d", S);
endmodule
module top;
parameter SIZE = 8;
mod #(SIZE) m();
endmodule
test/basic/paramtype_hier.sv deleted 100644 → 0
module Module #(
parameter int S,
parameter type T
);
T x;
if (S) begin : a
if (S) begin : b
assign Module.x = '1;
logic [$bits(Module.x):0] y = 'z;
end
end
initial $display("Module %0d: %b %0d %b %0d", S, Module.x, $bits(T), Module.a.b.y, $bits(Module.a.b.y));
endmodule
module top;
parameter ONE = 1;
logic [ONE*7:ONE*0] x;
if (1) begin : blk
localparam W = ONE * 3;
typedef logic [W-1:$bits(x)] T;
T x;
end
Module #(1, logic [$bits(x)-1:0]) m1();
Module #(2, logic [$bits(blk.x)-1:0]) m2();
Module #(3, logic [top.blk.W-1:0]) m3();
endmodule
test/basic/paramtype_hier.v deleted 100644 → 0
module Module;
parameter S = 0;
parameter T = 0;
wire [T-1:0] x;
generate
if (S) begin : a
if (S) begin : b
assign Module.x = 1'sb1;
wire [T:0] y = 1'sbz;
end
end
endgenerate
initial $display("Module %0d: %b %0d %b %0d", S, Module.x, T, Module.a.b.y, T + 1);
endmodule
module top;
parameter ONE = 1;
wire [ONE*7:ONE*0] x;
if (1) begin : blk
localparam W = ONE * 3;
wire [W-1:$bits(x)] x;
end
Module #(1, 8) m1();
Module #(2, 7) m2();
Module #(3, 3) m3();
endmodule
test/basic/paramtype_param.sv deleted 100644 → 0
package PKG;
typedef struct packed {
int W;
} F_t;
localparam F_t F_v = '{
W: 64
};
endpackage
module M0 #(
parameter type T,
parameter ID = "NONE"
);
T v;
initial $display("%s %0d %0d", ID, $bits(T), $bits(v));
endmodule
module M1 #(parameter PKG::F_t F = PKG::F_v) ();
typedef struct packed {
logic [F.W-1:0] field;
} local_t;
local_t v;
M0 #(.ID("A"), .T(local_t)) a();
M0 #(.ID("B"), .T(PKG::F_t)) b();
endmodule
module top;
typedef struct packed {
byte W;
} F_t;
localparam F_t F = '{
W: 16
};
typedef struct packed {
logic [F.W-1:0] field;
} local_t;
local_t v;
M1 m1();
M0 #(.ID("C"), .T(local_t)) c();
M0 #(.ID("D"), .T(PKG::F_t)) d();
M0 #(.ID("E"), .T(F_t)) e();
endmodule
test/basic/paramtype_param.v deleted 100644 → 0
module top;
localparam FORMAT = "%s %0d %0d";
initial begin
$display(FORMAT, "A", 64, 64);
$display(FORMAT, "B", 32, 32);
$display(FORMAT, "C", 16, 16);
$display(FORMAT, "D", 32, 32);
$display(FORMAT, "E", 8, 8);
end
endmodule
test/basic/paramtype_param_default.sv deleted 100644 → 0
module M #(
parameter ID = "Z",
parameter K = 2,
parameter type T = logic [K-1:0]
);
initial $display("%s %0d %0d", ID, K, $bits(T));
endmodule
module top;
M z();
M #(.ID("A")) a();
M #(.ID("B"), .K(3)) b();
M #(.ID("C"), .K(4)) c();
parameter K = 4;
localparam type T = logic [2*K-1:0];
M #(.ID("D"), .K(4), .T(T)) d();
endmodule
test/basic/paramtype_param_default.v deleted 100644 → 0
module M #(
parameter ID = "Z",
parameter K = 2,
parameter T = K
);
initial $display("%s %0d %0d", ID, K, T);
endmodule
module top;
M z();
M #(.ID("A")) a();
M #(.ID("B"), .K(3)) b();
M #(.ID("C"), .K(4)) c();
M #(.ID("D"), .K(4), .T(8)) d();
endmodule
test/basic/paramtype_recurse.sv deleted 100644 → 0
module foo #(
parameter type T = logic,
parameter size = 0
);
generate
if (size != 0) begin : foo
bar #(T, size - 1) x();
end
endgenerate
initial $display("foo %d %d", $bits(T), size);
endmodule
module bar #(
parameter type U = logic,
parameter size = 0
);
generate
if (size != 0) begin : bar
foo #(U, size - 1) x();
end
endgenerate
initial $display("bar %d %d", $bits(U), size);
endmodule
module top_1; foo #(byte, 2) x(); endmodule
module top_2; bar #(byte, 3) x(); endmodule
module top_3; foo #(bit, 4) x(); endmodule
module top_4; bar #(bit, 5) x(); endmodule
module top; foo x(); endmodule
test/basic/paramtype_recurse.v deleted 100644 → 0
module foo_byte #(
parameter size = 0
);
generate
if (size != 0) begin : foo
bar_byte #(size - 1) x();
end
endgenerate
initial $display("foo %d %d", 8, size);
endmodule
module bar_byte #(
parameter size = 0
);
generate
if (size != 0) begin : bar
foo_byte #(size - 1) x();
end
endgenerate
initial $display("bar %d %d", 8, size);
endmodule
module foo_bit #(
parameter size = 0
);
generate
if (size != 0) begin : foo
bar_bit #(size - 1) x();
end
endgenerate
initial $display("foo %d %d", 1, size);
endmodule
module bar_bit #(
parameter size = 0
);
generate
if (size != 0) begin : bar
foo_bit #(size - 1) x();
end
endgenerate
initial $display("bar %d %d", 1, size);
endmodule
module top_1; foo_byte #(2) x(); endmodule
module top_2; bar_byte #(3) x(); endmodule
module top_3; foo_bit #(4) x(); endmodule
module top_4; bar_bit #(5) x(); endmodule
module top; foo_bit #(0) x(); endmodule
test/basic/paramtype_struct_default.sv deleted 100644 → 0
module example(inp, data, valid);
parameter W = 16;
typedef struct packed {
logic [W-1:0] data;
logic valid;
} line_t;
parameter type local_line_t = line_t;
input local_line_t inp;
output logic [W-1:0] data;
assign data = inp.data;
output logic valid;
assign valid = inp.valid;
endmodule
module top;
reg [16:0] inp;
wire [15:0] data;
wire valid;
example e(.*);
initial inp = 17'b1_01100011_11001111;
endmodule
test/basic/paramtype_struct_default.v deleted 100644 → 0
module top;
reg [16:0] inp;
wire [15:0] data;
wire valid;
assign data = inp[16:1];
assign valid = inp[0];
initial inp = 17'b1_01100011_11001111;
endmodule
test/basic/part_select.sv deleted 100644 → 0
module top;
wire [31:0] a;
wire [0:31] b;
assign a = 'h64ded943, b = 'hb7151d17;
initial begin
$display(a[0+:8]);
$display(a[15-:8]);
$display(b[0+:8]);
$display(b[15-:8]);
end
endmodule
test/basic/part_select.v deleted 100644 → 0
module top;
wire [31:0] a;
wire [0:31] b;
assign a = 'h64ded943, b = 'hb7151d17;
initial begin
$display(a[7:0]);
$display(a[15:8]);
$display(b[0:7]);
$display(b[8:15]);
end
endmodule
test/basic/part_select_bits.sv deleted 100644 → 0
module top;
parameter A = 3;
parameter B = 4;
logic [A*B-1:0] arr;
initial begin
arr = 0;
for (integer i = 0; i < A; ++i) begin
// yes this is silly but it captures an interesting edge case
arr[i * B +: B] = $bits(arr[i * B +: B])'(i);
end
$display("%b", arr);
end
endmodule
test/basic/part_select_bits.v deleted 100644 → 0
module top;
parameter A = 3;
parameter B = 4;
reg [A*B-1:0] arr;
initial begin : foo
integer i;
arr = 0;
for (i = 0; i < A; ++i) begin
arr[i * B +: B] = i;
end
$display("%b", arr);
end
endmodule
test/basic/pattern.sv deleted 100644 → 0
module test;
typedef struct packed {
int w, x;
byte y;
logic z;
} struct_a;
struct_a a;
initial begin
$monitor("%2d: %b %b %b %b %b", $time, a, a.w, a.x, a.y, a.z);
#1 a.w = 0;
#1 a.x = 0;
#1 a.y = 0;
#1 a.z = 0;
#1 a = '{default: 1};
#1 a = '{default: 2};
#1 a = '{default: 3};
#1 a = '{default: 0};
#1 a = '{default: -1};
#1 a = '{default: -2};
#1 a = '{int: 0, default: 1};
#1 a = '{byte: 0, default: 1};
#1 a = '{logic: 0, default: 1};
#1 a = '{logic: 1, int: 2, byte: 3};
#1 a = '{logic: 1, int: 2, byte: 3, default: -1};
#1 a = '{int: 3, byte: 2, default: 0};
#1 a = '{w: 8, int: 0, default: 1};
#1 a = '{w: 8, byte: 0, default: 1};
#1 a = '{w: 8, logic: 0, default: 1};
#1 a = '{w: 8, logic: 1, int: 2, byte: 3};
#1 a = '{w: 8, logic: 1, int: 2, byte: 3, default: -1};
#1 a = '{w: 8, int: 3, byte: 2, default: 0};
end
typedef struct packed {
int x;
struct_a y;
logic z;
} struct_b;
struct_b b;
initial begin
#100;
$monitor("%2d: %b %b %b %b", $time, b, b.x, b.y, b.z);
#1 b.x = 0;
#1 b.y = 0;
#1 b.z = 0;
#1 b = '{default: 1};
#1 b = '{default: 2};
#1 b = '{default: 3};
#1 b = '{default: 0};
#1 b = '{default: -1};
#1 b = '{default: -2};
#1 b = '{int: 0, default: 1};
#1 b = '{byte: 0, default: 1};
#1 b = '{logic: 0, default: 1};
#1 b = '{logic: 1, int: 2, byte: 3};
#1 b = '{logic: 1, int: 2, byte: 3, default: -1};
#1 b = '{int: 3, byte: 2, default: 0};
end
endmodule
module top; endmodule
test/basic/pattern_revised.sv deleted 100644 → 0
module top;
parameter PARAM = 1;
`define BASE(expr, full, x, y, z) \
$display(`"%b %0d %0d %0d expr`", \
full, x, y, z)
`ifndef TEST
typedef byte T;
typedef struct packed {
byte x;
T y;
integer z;
} S;
`define TEST(a, b, c, expr) \
if (PARAM) begin \
S s; \
assign s = expr; \
initial `BASE(expr, s, s.x, s.y, s.z); \
end
`endif
`TEST(1, 2, 3, '{ x: 1, y: 2, z: 3 })
`TEST(2, 2, 3, '{ byte: 2, integer: 3 })
`TEST(3, 3, 2, '{ integer: 2, byte: 3 })
`TEST(4, 4, 2, '{ integer: 2, T: 4 })
`TEST(5, 5, 2, '{ integer: 2, T: 4, byte: 5 })
`TEST(5, 5, 2, '{ 2: 2, byte: 5 })
`TEST(7, 8, 9, '{ 1: 8, 2: 9, 0: 7 })
endmodule
test/basic/pattern_revised.v deleted 100644 → 0
`define TEST(aVal, bVal, cVal, expr) \
if (PARAM) begin \
wire [7:0] a, b; \
wire [31:0] c; \
assign a = aVal; \
assign b = bVal; \
assign c = cVal; \
initial `BASE(expr, {a, b, c}, a, b, c); \
end
`include "pattern_revised.sv"
test/basic/port_typename.sv deleted 100644 → 0
typedef wire b_t;
module top(
input a [1:0],
input b_t b
);
initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
endmodule
test/basic/port_typename.v deleted 100644 → 0
module top(
input [1:0] a,
input wire b
);
initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
endmodule
test/basic/reorder.sv deleted 100644 → 0
module top;
assign arr[0][0] = 1;
logic [1:0][2:0] arr;
initial $display("%b", arr);
parameter YES = 1;
if (YES) begin : blk
assign brr[0][0] = 1;
logic [2:0][3:0] brr;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0][0] = 1;
logic [3:0][4:0] crr;
initial $display("%b", crr);
end
end
endmodule
test/basic/reorder.v deleted 100644 → 0
module top;
wire [5:0] arr;
assign arr[0] = 1;
initial $display("%b", arr);
parameter YES = 1;
generate
if (YES) begin : blk
wire [11:0] brr;
assign brr[0] = 1;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0] = 1;
wire [19:0] crr;
initial $display("%b", crr);
end
end
endgenerate
endmodule
test/basic/shadow_recurse.sv deleted 100644 → 0
module top;
initial begin
logic x;
$display($bits(x));
begin
logic [0:$bits(x)] x;
$display($bits(x));
begin
logic [0:$bits(x)] x;
$display($bits(x));
end
end
end
initial begin
logic x;
$display($bits(type(x)));
begin
logic [0:$bits(type(x))] x;
$display($bits(type(x)));
begin
logic [0:$bits(type(x))] x;
$display($bits(type(x)));
end
end
end
initial begin
logic x;
$display($bits(x));
begin
logic [0:$bits(type(x))] x;
$display($bits(x));
begin
logic [0:$bits(type(x))] x;
$display($bits(x));
end
end
end
initial begin
logic x;
$display($bits(type(x)));
begin
logic [0:$bits(x)] x;
$display($bits(type(x)));
begin
logic [0:$bits(x)] x;
$display($bits(type(x)));
end
end
end
endmodule
test/basic/shadow_recurse.v deleted 100644 → 0
module top;
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
endmodule
test/basic/sign_cast.sv deleted 100644 → 0
module top;
initial begin
$display(signed'(4294967295));
$display(unsigned'(4294967295));
$display(signed'(-1));
$display(unsigned'(-1));
end
endmodule
test/basic/sign_cast.v deleted 100644 → 0
module top;
initial begin
$display($signed(4294967295));
$display($unsigned(4294967295));
$display($signed(-1));
$display($unsigned(-1));
end
endmodule
test/basic/simple_loop_jump.sv deleted 100644 → 0
module top;
function automatic integer f;
input integer inp;
f = 1;
for (integer idx = 0; idx < inp; idx = idx + 1) begin
if (f == 32)
break;
f = f * 2;
end
endfunction
function automatic integer g;
input integer inp;
integer idx;
g = 1;
for (idx = 0; idx < inp; idx = idx + 1) begin
if (g == 32)
break;
g = g * 2;
end
g += idx;
endfunction
function automatic integer h;
input integer inp;
integer idx;
h = 1;
for (idx = 0; idx + 1 < 1 + inp; idx = idx + 1) begin
if (h == 32)
break;
h = h * 2;
end
h += idx + 1;
endfunction
function automatic integer j;
input integer inp;
for (j = 0; j < inp; j = j + 1)
if (j == 3)
return j;
j *= 2;
endfunction
function automatic integer k;
input integer inp;
for (k = 0; k + 1 < 1 + inp; k = k + 1)
if (k == 3)
return k * 3;
k = k * 2 + 1;
endfunction
integer i;
initial
for (i = 0; i < 10; i = i + 1) begin
$display("f(%0d) = %0d", i, f(i));
$display("g(%0d) = %0d", i, g(i));
$display("h(%0d) = %0d", i, h(i));
$display("j(%0d) = %0d", i, j(i));
$display("k(%0d) = %0d", i, k(i));
end
endmodule
test/basic/simple_loop_jump.v deleted 100644 → 0
module top;
function automatic integer f;
input integer inp;
if (inp > 5)
f = 32;
else
f = 2 ** inp;
endfunction
function automatic integer g;
input integer inp;
if (inp > 5)
g = 32 + 5;
else
g = 2 ** inp + inp;
endfunction
function automatic integer h;
input integer inp;
if (inp > 5)
h = 32 + 5 + 1;
else
h = 2 ** inp + inp + 1;
endfunction
function automatic integer j;
input integer inp;
if (inp > 3)
j = 3;
else
j = inp * 2;
endfunction
function automatic integer k;
input integer inp;
if (inp > 3)
k = 3 * 3;
else
k = inp * 2 + 1;
endfunction
integer i;
initial
for (i = 0; i < 10; i = i + 1) begin
$display("f(%0d) = %0d", i, f(i));
$display("g(%0d) = %0d", i, g(i));
$display("h(%0d) = %0d", i, h(i));
$display("j(%0d) = %0d", i, j(i));
$display("k(%0d) = %0d", i, k(i));
end
endmodule
test/basic/simplify_func.sv deleted 100644 → 0
package PKG;
typedef struct packed {
int F;
} S;
function automatic S f();
return '0;
endfunction
endpackage
module top;
localparam PKG::S L0 = PKG::f();
localparam int L1 = L0.F;
localparam int L2 = $clog2(L1);
initial $display("%b %b %b", L0, L1, L2);
endmodule
test/basic/simplify_func.v deleted 100644 → 0
module top;
localparam L0 = 0;
localparam L1 = L0;
localparam L2 = $clog2(L1);
initial $display("%b %b %b", L0, L1, L2);
endmodule
test/basic/size_cast.sv deleted 100644 → 0
module top;
localparam BW = 3;
logic [2:0] test;
logic [3:0] foo;
logic [3:0] bar;
integer x;
reg [7:0] y;
initial begin
test = BW'(0);
$display(test);
foo = 2'('1);
$display(foo);
bar = $bits(bar)'('1);
$display(bar);
x = 1'('1); $display("%b %0d", x, x);
y = 1'('1); $display("%b %0d", y, y);
x = 2'('0); $display("%b %0d", x, x);
y = 2'('0); $display("%b %0d", y, y);
x = 2'('1); $display("%b %0d", x, x);
y = 2'('1); $display("%b %0d", y, y);
x = 2'('x); $display("%b %0d", x, x);
y = 2'('x); $display("%b %0d", y, y);
x = 2'('z); $display("%b %0d", x, x);
y = 2'('z); $display("%b %0d", y, y);
end
endmodule
test/basic/size_cast.v deleted 100644 → 0
module top;
reg [2:0] test;
reg [3:0] foo;
reg [3:0] bar;
integer x;
reg [7:0] y;
initial begin
test = 0;
$display(test);
foo = 4'b0011;
$display(foo);
bar = 4'b1111;
$display(bar);
x = 1'b1; $display("%b %0d", x, x);
y = 1'b1; $display("%b %0d", y, y);
x = 2'b00; $display("%b %0d", x, x);
y = 2'b00; $display("%b %0d", y, y);
x = 2'b11; $display("%b %0d", x, x);
y = 2'b11; $display("%b %0d", y, y);
x = 2'bxx; $display("%b %0d", x, x);
y = 2'bxx; $display("%b %0d", y, y);
x = 2'bzz; $display("%b %0d", x, x);
y = 2'bzz; $display("%b %0d", y, y);
end
endmodule
test/basic/stream.sv deleted 100644 → 0
module top;
// Derived from: https://www.amiq.com/consulting/2017/05/29/how-to-pack-data-using-systemverilog-streaming-operators/
typedef struct packed {
logic [3:0] addr;
logic [3:0] data;
} packet_t;
initial begin
logic [1:0] array[] = '{ 2'b10, 2'b01, 2'b11, 2'b00 };
packet_t packet = {<<4{ {<<2{array}} }};
$display("packet addr = %b", packet.addr);
$display("packet data = %b", packet.data);
end
initial begin
logic [23:0] temp;
temp = {>>byte{24'h060708}};
$display("%h", temp);
temp = {<<byte{24'h060708}};
$display("%h", temp);
temp = {>>bit{24'h060708}};
$display("%h", temp);
temp = {<<bit{24'h060708}};
$display("%h", temp);
temp = {>>7{24'h060708}};
$display("%h", temp);
temp = {<<7{24'h060708}};
$display("%h", temp);
temp = {>>7{20'h60708}};
$display("%h", temp);
temp = {<<7{20'h60708}};
$display("%h", temp);
temp = {>>7{16'h0708}};
$display("%h", temp);
temp = {<<7{16'h0708}};
$display("%h", temp);
end
task test_unpack;
input logic [23:0] in;
logic [0:0] i;
logic [1:0] j;
logic [2:0] k;
logic [5:0] l;
logic [11:0] m;
{>>byte{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<byte{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{>>bit{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<bit{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{>>7{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<7{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
endtask
initial begin
test_unpack(24'h060708);
test_unpack(24'hC02375);
test_unpack(24'h12E3B8);
end
endmodule
test/basic/stream_exhaust.sv deleted 100644 → 0
module Streamer(i, l1, r1, l2, r2);
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
input wire [IN_WIDTH-1:0] i;
output wire [OUT_WIDTH-1:0] l1;
output wire [OUT_WIDTH-1:0] r1;
output reg [OUT_WIDTH-1:0] l2;
output reg [OUT_WIDTH-1:0] r2;
if (IN_WIDTH <= OUT_WIDTH) begin
wire [OUT_WIDTH-1:0] lA = {<<CHUNK_SIZE{i}};
wire [OUT_WIDTH-1:0] rA = {>>CHUNK_SIZE{i}};
wire [OUT_WIDTH-1:0] lB;
wire [OUT_WIDTH-1:0] rB;
assign lB = {<<CHUNK_SIZE{i}};
assign rB = {>>CHUNK_SIZE{i}};
assign l1 = lA == lB ? lA : 'x;
assign r1 = rA == rB ? rA : 'x;
end
if (OUT_WIDTH <= IN_WIDTH) begin
always @* {<<CHUNK_SIZE{l2}} = i;
always @* {>>CHUNK_SIZE{r2}} = i;
end
endmodule
test/basic/stream_exhaust.v deleted 100644 → 0
module Streamer(i, l1, r1, l2, r2);
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
input wire [IN_WIDTH-1:0] i;
output wire [OUT_WIDTH-1:0] l1;
output wire [OUT_WIDTH-1:0] r1;
output reg [OUT_WIDTH-1:0] l2;
output reg [OUT_WIDTH-1:0] r2;
function [IN_WIDTH-1:0] stream_left;
input [IN_WIDTH-1:0] inp;
integer idx;
localparam remainder = IN_WIDTH % CHUNK_SIZE;
localparam remainder_fake = remainder ? remainder : 1;
begin
for (idx = 0; idx + CHUNK_SIZE <= IN_WIDTH; idx = idx + CHUNK_SIZE)
stream_left[IN_WIDTH - idx - 1 -: CHUNK_SIZE] = inp[idx+:CHUNK_SIZE];
if (remainder)
stream_left[0+:remainder_fake] = inp[idx+:remainder_fake];
end
endfunction
function [OUT_WIDTH-1:0] pad;
input [IN_WIDTH-1:0] inp;
pad = IN_WIDTH > OUT_WIDTH
? inp >> IN_WIDTH - OUT_WIDTH
: inp << OUT_WIDTH - IN_WIDTH
;
endfunction
generate
if (IN_WIDTH <= OUT_WIDTH) begin
assign l1 = pad(stream_left(i));
assign r1 = pad(i);
end
if (OUT_WIDTH <= IN_WIDTH) begin
always @* l2 = pad(stream_left(i));
always @* r2 = pad(i);
end
endgenerate
endmodule
test/basic/stream_exhaust_tb.v deleted 100644 → 0
module Tester;
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
reg [IN_WIDTH-1:0] i;
wire [OUT_WIDTH-1:0] l1, l2;
wire [OUT_WIDTH-1:0] r1, r2;
Streamer #(IN_WIDTH, OUT_WIDTH, CHUNK_SIZE)
streamer(i, l1, r1, l2, r2);
localparam DELAY = 8 * (CHUNK_SIZE + 8 * (OUT_WIDTH + 8 * IN_WIDTH));
initial #DELAY;
integer idx;
initial begin
for (idx = 0; idx < IN_WIDTH; idx = idx + 1) begin
i = 1 << idx;
#1 $display("INW=%0d OUTW=%0d CS=%0d i=%b l1=%b r1=%b l2=%b r2=%b",
IN_WIDTH, OUT_WIDTH, CHUNK_SIZE, i, l1, r1, l2, r2);
end
end
endmodule
module top;
generate
genvar i, o, c;
for (i = 1; i <= 8; i = i + 1)
for (o = 1; o <= 8; o = o + 1)
for (c = 1; c <= i; c = c + 1)
Tester #(i, o, c) tester();
endgenerate
endmodule
test/basic/string.sv deleted 100644 → 0
module top;
localparam FOO = "some useful string";
localparam type T = type(FOO);
localparam T BAR = "some other useful string"; // clipped
initial $display("'%s' '%s'", FOO, BAR);
endmodule
test/basic/string.v deleted 100644 → 0
module top;
localparam FOO = "some useful string";
localparam WIDTH = $bits("some useful string");
localparam [WIDTH-1:0] BAR = "some other useful string"; // clipped
initial $display("'%s' '%s'", FOO, BAR);
endmodule
test/basic/string_param.sv deleted 100644 → 0
`include "string_param.vh"
module Example(inp, out);
parameter PATTERN = "whatever";
parameter UNUSED = 0;
localparam IN_WIDTH = $bits(PATTERN);
localparam OUT_WIDTH = `COUNT_ONES(PATTERN);
input [IN_WIDTH - 1:0] inp;
output [OUT_WIDTH - 1:0] out;
if (PATTERN[0])
assign out[0] = inp[0];
for (genvar j = 1; j < IN_WIDTH; ++j)
if (PATTERN[j])
assign out[`COUNT_ONES(PATTERN[j - 1:0])] = inp[j];
endmodule
test/basic/string_param.v deleted 100644 → 0
`include "string_param.vh"
module Example(inp, out);
parameter PATTERN = "whatever";
parameter IN_WIDTH = $bits(PATTERN);
localparam OUT_WIDTH = `COUNT_ONES(PATTERN);
input wire [IN_WIDTH - 1:0] inp;
output wire [OUT_WIDTH - 1:0] out;
if (PATTERN[0])
assign out[0] = inp[0];
genvar j;
for (j = 1; j < IN_WIDTH; j = j + 1)
if (PATTERN[j])
assign out[`COUNT_ONES(PATTERN[j - 1:0])] = inp[j];
endmodule
test/basic/string_param.vh deleted 100644 → 0
`define COUNT_ONES(expr) (0 \
+ ((expr) >> 0 & 1'b1) + ((expr) >> 1 & 1'b1) + ((expr) >> 2 & 1'b1) + ((expr) >> 3 & 1'b1) \
+ ((expr) >> 4 & 1'b1) + ((expr) >> 5 & 1'b1) + ((expr) >> 6 & 1'b1) + ((expr) >> 7 & 1'b1) \
+ ((expr) >> 8 & 1'b1) + ((expr) >> 9 & 1'b1) + ((expr) >> 10 & 1'b1) + ((expr) >> 11 & 1'b1) \
+ ((expr) >> 12 & 1'b1) + ((expr) >> 13 & 1'b1) + ((expr) >> 14 & 1'b1) + ((expr) >> 15 & 1'b1) \
+ ((expr) >> 16 & 1'b1) + ((expr) >> 17 & 1'b1) + ((expr) >> 18 & 1'b1) + ((expr) >> 19 & 1'b1) \
+ ((expr) >> 20 & 1'b1) + ((expr) >> 21 & 1'b1) + ((expr) >> 22 & 1'b1) + ((expr) >> 23 & 1'b1) \
+ ((expr) >> 24 & 1'b1) + ((expr) >> 25 & 1'b1) + ((expr) >> 26 & 1'b1) + ((expr) >> 27 & 1'b1) \
+ ((expr) >> 28 & 1'b1) + ((expr) >> 29 & 1'b1) + ((expr) >> 30 & 1'b1) + ((expr) >> 31 & 1'b1) \
)
module top;
reg [31:0] data;
`define TEST(idx, pattern, in_width, out_width) \
localparam p``idx = pattern; \
wire [in_width - 1:0] i``idx; \
wire [out_width - 1:0] o``idx; \
assign i``idx = data[0+:in_width]; \
Example #(p``idx, in_width) e``idx(i``idx, o``idx);
`TEST(1, 5'b10101, 5, 3)
`TEST(2, 10'b1110001111, 10, 7)
integer i;
initial begin
data = 0;
for (i = 0; i < 100; i = i + 1) begin
data = 1664525 * data + 1013904223;
#1 $display("%b %b %b", data, o1, o2);
end
end
endmodule
test/basic/struct_array.sv deleted 100644 → 0
typedef struct packed {
logic x;
logic [3:0] y;
logic [1:0] z;
} Struct_t;
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input Struct_t [WIDTH-1:0] in;
input logic [$clog2(WIDTH)-1:0] select;
output logic a;
output logic [3:0] b;
output logic [1:0] c;
assign a = in[select].x;
assign b = in[select].y;
assign c = in[select].z;
endmodule
test/basic/struct_array.v deleted 100644 → 0
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input wire [WIDTH*7-1:0] in;
input wire [$clog2(WIDTH)-1:0] select;
output wire a;
output wire [3:0] b;
output wire [1:0] c;
wire [6:0] p;
assign p = in[select*7+:7];
assign a = p[6:6];
assign b = p[5:2];
assign c = p[1:0];
endmodule
test/basic/struct_array_field.sv deleted 100644 → 0
module main;
typedef struct packed {
logic [1:0][2:0] x;
logic [0:2][1:0] y;
logic z;
} foo_t;
foo_t foo;
initial begin
$monitor($time, " %b %b %b %b %b %b %b %b",
foo, foo.x, foo.y, foo.z,
foo.x[0], foo.x[0][0], foo.y[0], foo.y[0][0]);
#1; foo.z = 0;
#1; foo.y = 0;
#1; foo.y[0] = '1;
#1; foo.y[1] = '1;
#1; foo.y[1][1] = 0;
#1; foo.y[0][0] = 1;
#1; foo.y[0][1] = 1;
#1; foo.x = 0;
#1; foo.x[0] = '1;
#1; foo.x[1] = '1;
#1; foo.x[1][1] = 0;
#1; foo.x[0][0] = 1;
#1; foo.x[0][1] = 1;
end
endmodule
module top;
endmodule
test/basic/struct_array_field.v deleted 100644 → 0
module main;
reg [2:0] foo_x_1;
reg [2:0] foo_x_0;
reg [1:0] foo_y_2;
reg [1:0] foo_y_1;
reg [1:0] foo_y_0;
wire [5:0] foo_x;
wire [5:0] foo_y;
assign foo_x = {foo_x_1, foo_x_0};
assign foo_y = {foo_y_0, foo_y_1, foo_y_2};
reg foo_z;
wire [12:0] foo;
assign foo = {foo_x, foo_y, foo_z};
initial begin
$monitor($time, " %b %b %b %b %b %b %b %b",
foo, foo_x, foo_y, foo_z,
foo_x_0, foo_x_0[0], foo_y_0, foo_y_0[0]);
#1; foo_z = 0;
#1; {foo_y_0, foo_y_1, foo_y_2} = 0;
#1; foo_y_0 = 1'sb1;
#1; foo_y_1 = 1'sb1;
#1; foo_y_1[1] = 0;
#1; foo_y_0[0] = 1;
#1; foo_y_0[1] = 1;
#1; {foo_x_1, foo_x_0} = 0;
#1; foo_x_0 = 1'sb1;
#1; foo_x_1 = 1'sb1;
#1; foo_x_1[1] = 0;
#1; foo_x_0[0] = 1;
#1; foo_x_0[1] = 1;
end
endmodule
module top;
endmodule
test/basic/struct_array_inline.sv deleted 100644 → 0
module top;
typedef struct packed {
bit a, b;
} T;
localparam T FOO [4] = '{
'{ 0, 0 },
'{ 0, 1 },
'{ 1, 0 },
'{ 1, 1 }
};
initial begin
$display(FOO[0].a);
$display(FOO[0].b);
$display(FOO[2].a);
$display(FOO[2].b);
end
endmodule
test/basic/struct_array_inline.v deleted 100644 → 0
module top;
initial begin
$display(1'b0);
$display(1'b0);
$display(1'b1);
$display(1'b0);
end
endmodule
test/basic/struct_array_param.sv deleted 100644 → 0
typedef struct packed {
logic [2:0] a;
logic [1:0] b;
logic [3:0] c;
} foo_s;
parameter foo_s [1:0] foo = {
'{ a: 2, b: 1, c: 0 },
'{ a: 1, b: 0, c: 2 }
};
module top;
initial begin
$display(foo[0]);
$display(foo[1]);
end
endmodule
test/basic/struct_array_param.v deleted 100644 → 0
module top;
parameter foo_1 = { 3'b010, 2'b01, 4'b0000 };
parameter foo_0 = { 3'b001, 2'b00, 4'b0010 };
initial begin
$display(foo_0);
$display(foo_1);
end
endmodule
test/basic/struct_array_tb.v deleted 100644 → 0
module top;
reg [56-1:0] in;
reg [2:0] select;
wire a;
wire [3:0] b;
wire [1:0] c;
Unpacker unpacker(in, select, a, b, c);
initial begin
$monitor("%d: %01b %04b %02b", select, a, b, c);
in = 'b01111011011011101111100111110111001010001011100110101000;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
select = 4; #1;
select = 5; #1;
select = 6; #1;
select = 7; #1;
$finish;
end
// 0 1010 00
// 1 1100 11
// 0 1000 10
// 0 1110 01
// 0 0111 11
// 1 0111 11
// 1 0110 11
// 0 1111 01
endmodule
test/basic/struct_bit_struct.sv deleted 100644 → 0
typedef struct packed {
logic [3:0] a;
logic [3:0] b;
} pair;
typedef struct packed {
pair [1:0] x;
pair [1:0] y;
} pair_list_pair;
module Example(data, p1, p2, out_x, out_y);
input pair_list_pair data;
input logic p1;
input logic p2;
output logic [3:0] out_x;
output logic [3:0] out_y;
assign out_x = p2 ? data.x[p1].a : data.x[p1].b;
assign out_y = p2 ? data.y[p1].a : data.y[p1].b;
endmodule
test/basic/struct_bit_struct.v deleted 100644 → 0
module Example(data, p1, p2, out_x, out_y);
input wire [31:0] data;
input wire p1, p2;
output wire [3:0] out_x;
output wire [3:0] out_y;
assign out_x = p2 ? data[p1 * 8 + 20 +:4] : data[p1 * 8 + 16 +:4];
assign out_y = p2 ? data[p1 * 8 + 4 +:4] : data[p1 * 8 + 0 +:4];
endmodule
test/basic/struct_bit_struct_tb.v deleted 100644 → 0
module top;
reg [31:0] data;
reg p1, p2;
wire [3:0] out_x;
wire [3:0] out_y;
Example example(data, p1, p2, out_x, out_y);
task exhaust;
begin
#1 p1 = 0;
#1 p2 = 0;
#1 p1 = 0;
#1 p2 = 1;
#1 p1 = 1;
#1 p2 = 0;
#1 p1 = 1;
#1 p2 = 1;
end
endtask
initial begin
$monitor("%2d %b %b %b %b %b", $time,
data, p1, p2, out_x, out_y);
#1 data = 32'ha7107338;
exhaust;
#1 data = 32'h8f8259e4;
exhaust;
#1 data = 32'h80ad046a;
exhaust;
#1 data = 32'hbf93017e;
exhaust;
#1 data = 32'he6458a2d;
exhaust;
end
endmodule
test/basic/struct_default.sv deleted 100644 → 0
module top;
typedef struct packed {
logic a;
logic b;
} foo_t;
foo_t foo;
initial begin
foo = '{a: 1'b1, default: '0};
$display(foo, foo.a, foo.b);
end
endmodule
test/basic/struct_default.v deleted 100644 → 0
module top;
reg [1:0] foo = {1'b1, 1'b0};
initial $display(foo, foo[1], foo[0]);
endmodule
test/basic/struct_hier_bit.sv deleted 100644 → 0
module top;
if (1) begin : blk
struct packed {
logic x, y;
} [1:0] s;
end
assign blk.s[0].x = 0;
assign top.blk.s[0].y = 1;
assign top.blk.s[1].x = 1;
assign blk.s[1].y = 0;
initial #1 $display("%b", blk.s);
endmodule
test/basic/struct_hier_bit.v deleted 100644 → 0
module top;
if (1) begin : blk
wire [3:0] s;
end
assign blk.s = 4'b1001;
initial #1 $display("%b", blk.s);
endmodule
test/basic/struct_ident_scope.sv deleted 100644 → 0
`define DUMP(id) \
begin \
x = 1'sb1; \
$display(`"id: access a=%b b=%b`", x.a, x.b); \
x = '{ a: 1'sb1, b: 1'sbz }; \
$display(`"id: literal x=%b`", x); \
end
module top;
parameter A = 2;
parameter B = 3;
struct packed {
logic [A-1:0] a;
logic [B-1:0] b;
} x;
initial `DUMP(0)
if (1) begin : blk
localparam A = 10;
localparam B = 11;
initial `DUMP(1)
end
initial begin
localparam A = 10;
localparam B = 11;
`DUMP(2)
end
endmodule
test/basic/struct_ident_scope.v deleted 100644 → 0
`define DUMP(id) \
begin \
x = 1'sb1; \
$display(`"id: access a=%b b=%b`", x[0+:A], x[A+:B]); \
x = { {A {1'sb1}}, {B {1'sbz}} }; \
$display(`"id: literal x=%b`", x); \
end
module top;
parameter A = 2;
parameter B = 3;
reg [A+B-1:0] x;
initial `DUMP(0)
if (1) begin : blk
localparam _A = 10;
localparam _B = 11;
initial `DUMP(1)
end
initial begin : foo
localparam _A = 10;
localparam _B = 11;
`DUMP(2)
end
endmodule
test/basic/struct_integer.sv deleted 100644 → 0
module top;
typedef struct packed {
integer a, b, c;
} S;
S s = '{a: 1, b: 2, c: 3};
initial #1 $display("%b %b %b %b", s, s.a, s.b, s.c);
endmodule
test/basic/struct_integer.v deleted 100644 → 0
module top;
wire [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
endmodule
test/basic/struct_nested_cast.sv deleted 100644 → 0
package PKG;
typedef struct packed {
logic f;
} foo_t;
endpackage
module top;
typedef struct packed {
PKG::foo_t f;
} local_t;
local_t w;
initial begin
w <= local_t'(1'sb1);
$display("%b", w);
end
endmodule
test/basic/struct_nested_cast.v deleted 100644 → 0
module top;
reg w;
initial begin
w <= 1'b1;
$display("%b", w);
end
endmodule
test/basic/struct_param.sv deleted 100644 → 0
module Module #(parameter type T, parameter N);
T t;
type(t.a) x;
type(t.b) y;
initial begin
$display("$bits(T)=", $bits(T));
$display("$bits(t)=", $bits(t));
$display("$bits(t.a)=", $bits(t.a));
$display("$bits(t.b)=", $bits(t.b));
$display("$bits(x)=", $bits(x));
$display("$bits(y)=", $bits(y));
$display("$bits(N)=", $bits(N));
$display("N=", N);
end
endmodule
module top;
typedef struct packed {
logic a;
logic [2] b;
} Struct1;
typedef struct packed {
logic [5] a;
Struct1 b;
logic [2] c;
logic d;
} Struct2;
Module #(Struct1, $bits(Struct1)) m1();
Module #(Struct2, $bits(Struct2)) m2();
endmodule
test/basic/struct_param.v deleted 100644 → 0
module Module1 #(parameter N = 1);
initial begin
$display("$bits(T)=", 3);
$display("$bits(t)=", 3);
$display("$bits(t.a)=", 1);
$display("$bits(t.b)=", 2);
$display("$bits(x)=", 1);
$display("$bits(y)=", 2);
$display("$bits(N)=", 32);
$display("N=", N);
end
endmodule
module Module2 #(parameter N = 1);
initial begin
$display("$bits(T)=", 11);
$display("$bits(t)=", 11);
$display("$bits(t.a)=", 5);
$display("$bits(t.b)=", 3);
$display("$bits(x)=", 5);
$display("$bits(y)=", 3);
$display("$bits(N)=", 32);
$display("N=", N);
end
endmodule
module top;
Module1 #(3) m1();
Module2 #(11) m2();
endmodule
test/basic/struct_part_select.sv deleted 100644 → 0
module Example;
typedef struct packed {
logic [10:4] a;
logic [1:3] bx;
logic [3:1] by;
logic [3:4][5:7] cw;
logic [4:3][5:7] cx;
logic [3:4][7:5] cy;
logic [4:3][7:5] cz;
} T;
T t;
initial begin
$monitor("%2d %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b", $time,
t, t.a, t.bx, t.by,
t.cw, t.cw[3], t.cw[4],
t.cx, t.cx[3], t.cx[4],
t.cy, t.cy[3], t.cy[4],
t.cz, t.cz[3], t.cz[4]
);
#1 t.a = 1;
#1 t.a[5+:2] = '1;
#1 t.a[8-:3] = '1;
#1 t.a[10] = 1;
#1 t.a[7] = 0;
#1 t.bx[1+:1] = 1;
#1 t.bx[1:2] = 1;
#1 t.bx[3] = 0;
#1 t.bx[3-:2] = 1;
#1 t.bx[2] = 0;
#1 t.by[1+:1] = 1;
#1 t.by[2:1] = 1;
#1 t.by[3] = 0;
#1 t.by[3-:2] = 1;
#1 t.by[2] = 0;
#1 t.cw[3][6+:1] = 1;
#1 t.cw[3][7-:2] = 1;
#1 t.cw[3][5+:2] = 0;
#1 t.cw[3][6:7] = 2'b10;
#1 t.cw[3][6:7] = 2'b01;
#1 t.cw[3:4] = '1;
#1 t.cw[4][5] = 0;
#1 t.cw[4][6:7] = 0;
#1 t.cw[3+:2] = 6'b010011;
#1 t.cw[4-:2] = 6'b101011;
#1 t.cx[3][6+:1] = 1;
#1 t.cx[3][7-:2] = 1;
#1 t.cx[3][5+:2] = 0;
#1 t.cx[3][6:7] = 2'b10;
#1 t.cx[3][6:7] = 2'b01;
#1 t.cx[4:3] = '1;
#1 t.cx[4][5] = 0;
#1 t.cx[4][6:7] = 0;
#1 t.cx[3+:2] = 6'b010011;
#1 t.cx[4-:2] = 6'b101011;
#1 t.cy[3][6+:1] = 1;
#1 t.cy[3][7-:2] = 1;
#1 t.cy[3][5+:2] = 0;
#1 t.cy[3][7:6] = 2'b10;
#1 t.cy[3][7:6] = 2'b01;
#1 t.cy[3:4] = '1;
#1 t.cy[4][5] = 0;
#1 t.cy[4][7:6] = 0;
#1 t.cy[3+:2] = 6'b010011;
#1 t.cy[4-:2] = 6'b101011;
#1 t.cz[3][6+:1] = 1;
#1 t.cz[3][7-:2] = 1;
#1 t.cz[3][5+:2] = 0;
#1 t.cz[3][7:6] = 2'b10;
#1 t.cz[3][7:6] = 2'b01;
#1 t.cz[4:3] = '1;
#1 t.cz[4][5] = 0;
#1 t.cz[4][7:6] = 0;
#1 t.cz[3+:2] = 6'b010011;
#1 t.cz[4-:2] = 6'b101011;
end
endmodule
module top;
endmodule
test/basic/struct_part_select_param.v deleted 100644 → 0
// The reference output for this test should match that of the
// struct_part_select test.
`include "struct_part_select.v"
test/basic/struct_scope.sv deleted 100644 → 0
module top;
typedef struct packed {
logic x;
logic [1:0] y;
} A;
typedef struct packed {
logic [2:0] x;
logic [3:0] y;
} B;
typedef struct packed {
logic [4:0] x;
logic [5:0] y;
B z;
} C;
A a;
B b;
C c;
generate
begin : foo
typedef struct packed {
logic [6:0] x;
logic [7:0] y;
} B;
typedef struct packed {
logic [8:0] x;
logic [9:0] y;
B z;
} D;
A a;
B b;
C c;
D d;
end
endgenerate
`define INSPECT_SIZE(expr) $display(`"expr -> %0d`", $bits(expr));
`define INSPECT_DATA(expr) $display(`"expr -> %b`", expr);
initial begin
`INSPECT_SIZE(a);
`INSPECT_SIZE(a.x);
`INSPECT_SIZE(a.y);
`INSPECT_SIZE(b);
`INSPECT_SIZE(b.x);
`INSPECT_SIZE(b.y);
`INSPECT_SIZE(c);
`INSPECT_SIZE(c.x);
`INSPECT_SIZE(c.y);
`INSPECT_SIZE(c.z);
`INSPECT_SIZE(c.z.x);
`INSPECT_SIZE(c.z.y);
`INSPECT_SIZE(foo.a);
`INSPECT_SIZE(foo.a.x);
`INSPECT_SIZE(foo.a.y);
`INSPECT_SIZE(foo.b);
`INSPECT_SIZE(foo.b.x);
`INSPECT_SIZE(foo.b.y);
`INSPECT_SIZE(foo.c);
`INSPECT_SIZE(foo.c.x);
`INSPECT_SIZE(foo.c.y);
`INSPECT_SIZE(foo.c.z);
`INSPECT_SIZE(foo.c.z.x);
`INSPECT_SIZE(foo.c.z.y);
`INSPECT_SIZE(foo.d);
`INSPECT_SIZE(foo.d.x);
`INSPECT_SIZE(foo.d.y);
`INSPECT_SIZE(foo.d.z);
`INSPECT_SIZE(foo.d.z.x);
`INSPECT_SIZE(foo.d.z.y);
`INSPECT_DATA(a);
`INSPECT_DATA(b);
`INSPECT_DATA(c);
`INSPECT_DATA(foo.a);
`INSPECT_DATA(foo.b);
`INSPECT_DATA(foo.c);
`INSPECT_DATA(foo.d);
end
endmodule
test/basic/struct_scope.v deleted 100644 → 0
module top;
wire [2:0] a;
wire [6:0] b;
wire [17:0] c;
generate
if (1) begin : foo
wire [2:0] a;
wire [14:0] b;
wire [17:0] c;
wire [33:0] d;
end
endgenerate
`define INSPECT_SIZE(expr, size) $display(`"expr -> %0d`", size);
`define INSPECT_DATA(expr) $display(`"expr -> %b`", expr);
initial begin
`INSPECT_SIZE(a, 3);
`INSPECT_SIZE(a.x, 1);
`INSPECT_SIZE(a.y, 2);
`INSPECT_SIZE(b, 7);
`INSPECT_SIZE(b.x, 3);
`INSPECT_SIZE(b.y, 4);
`INSPECT_SIZE(c, 18);
`INSPECT_SIZE(c.x, 5);
`INSPECT_SIZE(c.y, 6);
`INSPECT_SIZE(c.z, 7);
`INSPECT_SIZE(c.z.x, 3);
`INSPECT_SIZE(c.z.y, 4);
`INSPECT_SIZE(foo.a, 3);
`INSPECT_SIZE(foo.a.x, 1);
`INSPECT_SIZE(foo.a.y, 2);
`INSPECT_SIZE(foo.b, 15);
`INSPECT_SIZE(foo.b.x, 7);
`INSPECT_SIZE(foo.b.y, 8);
`INSPECT_SIZE(foo.c, 18);
`INSPECT_SIZE(foo.c.x, 5);
`INSPECT_SIZE(foo.c.y, 6);
`INSPECT_SIZE(foo.c.z, 7);
`INSPECT_SIZE(foo.c.z.x, 3);
`INSPECT_SIZE(foo.c.z.y, 4);
`INSPECT_SIZE(foo.d, 34);
`INSPECT_SIZE(foo.d.x, 9);
`INSPECT_SIZE(foo.d.y, 10);
`INSPECT_SIZE(foo.d.z, 15);
`INSPECT_SIZE(foo.d.z.x, 7);
`INSPECT_SIZE(foo.d.z.y, 8);
`INSPECT_DATA(a);
`INSPECT_DATA(b);
`INSPECT_DATA(c);
`INSPECT_DATA(foo.a);
`INSPECT_DATA(foo.b);
`INSPECT_DATA(foo.c);
`INSPECT_DATA(foo.d);
end
endmodule
test/basic/struct_shadow.v deleted 100644 → 0
// While this might look silly, you'll notice that the sections are actually
// different. We are ensuring that the correct struct definitions are being used
// in each scope.
module top;
reg [2:0] a = 3'b111;
reg [2:0] b = 3'b111;
reg [2:0] c = 3'b111;
reg [2:0] d = 3'b111;
reg [2:0] e = 3'b111;
reg [2:0] f = 3'b111;
integer i = 2;
integer j = 2;
integer k = 2;
initial begin
$display("A: 000 -> 000000");
$display("A: 001 -> 121424");
$display("A: 010 -> 214142");
$display("A: 011 -> 335566");
$display("A: 100 -> 442211");
$display("A: 101 -> 563635");
$display("A: 110 -> 656353");
$display("A: 111 -> 777777");
$display("B: 000 -> 000000");
$display("B: 001 -> 214241");
$display("B: 010 -> 141422");
$display("B: 011 -> 355663");
$display("B: 100 -> 422114");
$display("B: 101 -> 636355");
$display("B: 110 -> 563536");
$display("B: 111 -> 777777");
$display("C: 000 -> 000000");
$display("C: 001 -> 142412");
$display("C: 010 -> 414221");
$display("C: 011 -> 556633");
$display("C: 100 -> 221144");
$display("C: 101 -> 363556");
$display("C: 110 -> 635365");
$display("C: 111 -> 777777");
$display("D: 000 -> 000000");
$display("D: 001 -> 424121");
$display("D: 010 -> 142214");
$display("D: 011 -> 566335");
$display("D: 100 -> 211442");
$display("D: 101 -> 635563");
$display("D: 110 -> 353656");
$display("D: 111 -> 777777");
$display("E: 000 -> 000000");
$display("E: 001 -> 241214");
$display("E: 010 -> 422141");
$display("E: 011 -> 663355");
$display("E: 100 -> 114422");
$display("E: 101 -> 355636");
$display("E: 110 -> 536563");
$display("E: 111 -> 777777");
$display("F: 000 -> 000000");
$display("F: 001 -> 412142");
$display("F: 010 -> 221414");
$display("F: 011 -> 633556");
$display("F: 100 -> 144221");
$display("F: 101 -> 556363");
$display("F: 110 -> 365635");
$display("F: 111 -> 777777");
end
endmodule
test/basic/struct_tern.sv deleted 100644 → 0
module Example(flag, out);
typedef struct packed {
logic a, b;
} T;
output T out;
input logic flag;
assign out =
flag
? '{ a: 1'b1, b: 1'b0 }
: '{ a: 1'b1, b: 1'b1 }
;
endmodule
test/basic/struct_tern.v deleted 100644 → 0
module Example(flag, out);
output wire [1:0] out;
input wire flag;
assign out = flag ? 2'b10 : 2'b11;
endmodule
test/basic/struct_tern_tb.v deleted 100644 → 0
module top;
reg flag;
wire [1:0] out;
Example example(flag, out);
initial begin
$monitor("%2d %b %b", $time, flag, out);
#1 flag = 0;
#1 flag = 1;
#1 flag = 0;
#1 flag = 1;
end
endmodule
test/basic/struct_unit_array.sv deleted 100644 → 0
module top;
typedef struct packed {
logic a, b;
} T;
typedef struct packed {
logic x;
T y;
} S;
localparam WIDTH = 1;
S [WIDTH] s = '{
'{x: 1, y: '{a: 1, b: 0}}
};
initial #1 $display("%b", s);
endmodule
test/basic/struct_unit_array.v deleted 100644 → 0
module top;
wire [2:0] s = 3'b110;
initial #1 $display("%b", s);
endmodule
test/basic/subroutine.sv deleted 100644 → 0
class C #(
parameter X = 1
);
static task dump;
$display("C#(%0d)::dump()", X);
endtask
endclass
package P;
task dump;
$display("P::dump()");
endtask
endpackage
module top;
task dump;
$display("dump()");
endtask
`define TEST(subroutine) \
initial begin subroutine; end \
initial begin subroutine(); end \
initial begin ; subroutine; end \
initial begin ; subroutine(); end
`TEST(dump)
`TEST(P::dump)
`TEST(C#(1)::dump)
endmodule
test/basic/subroutine.v deleted 100644 → 0
module top;
`define TEST(subroutine) \
initial repeat (4) $display(`"subroutine()`");
`TEST(dump)
`TEST(P::dump)
`TEST(C#(1)::dump)
endmodule
test/basic/tf_block.sv deleted 100644 → 0
module top;
function [2:0] f;
input [2:0] n;
n += 1;
return n + 3;
endfunction
task t;
$display("hello");
$display("world");
endtask
initial t();
initial $display("f(0) = ", f(0));
initial $display("f(1) = ", f(1));
endmodule
test/basic/tf_block.v deleted 100644 → 0
module top;
function [2:0] f;
input [2:0] n;
f = n + 4;
endfunction
task t;
begin
$display("hello");
$display("world");
end
endtask
initial t();
initial $display("f(0) = ", f(0));
initial $display("f(1) = ", f(1));
endmodule
test/basic/time.sv deleted 100644 → 0
`timescale 1ns / 10ps
timeunit 100ps;
timeprecision 1ps;
module top_1;
`timescale 1ns / 10ps
timeunit 1ps;
timeprecision 1ps;
endmodule
module top_2;
timeunit 100ps / 10fs;
endmodule
module top_3;
timeunit 10.0ps / 10fs;
endmodule
module top_4;
timeunit 100ps;
timeprecision 10fs;
endmodule
module top;
initial $display("Hello!");
endmodule
test/basic/time.v deleted 100644 → 0
module top;
initial $display("Hello!");
endmodule
test/basic/top_tf.sv deleted 100644 → 0
task foo;
$display("task foo() called");
endtask
function bar;
input [2:0] n;
bar = baz(n + 1);
endfunction
function baz;
input [2:0] n;
baz = n * 2;
endfunction
localparam PARAM = 37;
module top;
initial foo();
initial $display("bar(0) = %d", bar(0));
initial $display("PARAM = %d", PARAM);
endmodule
test/basic/top_tf.v deleted 100644 → 0
module top;
task foo;
$display("task foo() called");
endtask
function bar;
input [2:0] n;
bar = baz(n + 1);
endfunction
function baz;
input [2:0] n;
baz = n * 2;
endfunction
localparam PARAM = 37;
initial foo();
initial $display("bar(0) = %d", bar(0));
initial $display("PARAM = %d", PARAM);
endmodule
test/basic/trailing_commas.sv deleted 100644 → 0
module ModuleA #(P=1,) (inp,);
input inp;
initial $display("ModuleA P=%0d inp=%b", P, inp);
endmodule
module ModuleB #(parameter P,) (input inp,);
initial $display("ModuleB P=%0d inp=%b", P, inp);
endmodule
module top;
ModuleA #(1,) a(1'b1,);
ModuleB #(.P(1),) b(.inp(1'b1),);
endmodule
test/basic/trailing_commas.v deleted 100644 → 0
module ModuleA #(parameter P = 1) (input inp);
initial $display("ModuleA P=%0d inp=%b", P, inp);
endmodule
module ModuleB #(parameter P = 0) (input inp);
initial $display("ModuleB P=%0d inp=%b", P, inp);
endmodule
module top;
ModuleA #(1) a(1'b1);
ModuleB #(.P(1)) b(.inp(1'b1));
endmodule
test/basic/typedef_ident_scope.sv deleted 100644 → 0
`define DUMP(id) \
$display(`"id: $bits(T) = %0d, $left(T) = %0d, $right(T) = %0d`", \
$bits(T), $left(T), $right(T))
module top;
parameter A = 1;
parameter B = 2;
parameter ONE = 1;
typedef logic [A:B] T;
initial `DUMP(X1);
if (1) begin : blk
localparam A = ONE * 3;
localparam B = ONE * 4;
initial `DUMP(X2);
if (1) begin : nest
typedef logic [A:B] T;
initial `DUMP(Y0);
end
end
initial begin
localparam A = ONE * 5;
localparam B = ONE * 6;
`DUMP(X3);
begin
localparam type T = logic [A:B];
`DUMP(Z0);
end
end
endmodule
test/basic/typedef_ident_scope.v deleted 100644 → 0
`define DUMP(id, A, B) \
$display(`"id: $bits(T) = %0d, $left(T) = %0d, $right(T) = %0d`", \
A >= B ? A - B + 1: B - A + 1, A, B)
module top;
parameter A = 1;
parameter B = 2;
parameter ONE = 1;
initial `DUMP(X1, A, B);
if (1) begin : blk
localparam _A = ONE * 3;
localparam _B = ONE * 4;
initial `DUMP(X2, A, B);
if (1) begin : nest
initial `DUMP(Y0, _A, _B);
end
end
initial begin : foo
localparam _A = ONE * 5;
localparam _B = ONE * 6;
`DUMP(X3, A, B);
`DUMP(Z0, _A, _B);
end
endmodule
test/basic/typedef_scope.sv deleted 100644 → 0
module Example;
parameter FLAG_1 = 0;
parameter FLAG_2 = 0;
typedef logic [2:0] T;
if (FLAG_1) begin
typedef logic [1:0] T;
T t = 0;
initial $display("2 %b", t);
if (FLAG_2) begin
typedef logic [3:0] T;
T t = 0;
initial $display("4 %b", t);
end
end
else begin
typedef logic T;
T t = 0;
initial $display("1 %b", t);
end
T t = 0;
initial $display("3 %b", t);
endmodule
module top;
Example #(0, 0) a();
Example #(1, 0) b();
Example #(0, 1) c();
Example #(1, 1) d();
endmodule
test/basic/typedef_scope.v deleted 100644 → 0
module Example;
parameter FLAG_1 = 0;
parameter FLAG_2 = 0;
if (FLAG_1) begin
wire [1:0] t = 0;
initial $display("2 %b", t);
if (FLAG_2) begin
wire [3:0] t = 0;
initial $display("4 %b", t);
end
end
else begin
wire t = 0;
initial $display("1 %b", t);
end
wire [2:0] t = 0;
initial $display("3 %b", t);
endmodule
module top;
Example #(0, 0) a();
Example #(1, 0) b();
Example #(0, 1) c();
Example #(1, 1) d();
endmodule
test/basic/typename_cast.sv deleted 100644 → 0
module Example;
parameter type T = logic [3:0];
T v = T'('1);
initial #1 $display("%b", v);
endmodule
module top; Example example(); endmodule
test/basic/typename_cast.v deleted 100644 → 0
module Example;
wire [3:0] v = 4'b1111;
initial #1 $display("%b", v);
endmodule
module top; Example example(); endmodule
test/basic/typeof.sv deleted 100644 → 0
module top;
function f;
input x;
f = 1'b1 ^ x;
$display("f(%b) called", x);
endfunction
task t;
input x;
$display("t(%b) called", x);
endtask
initial begin
type(f(0)) x = f(0);
type(x) y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", $bits(x));
$display("%b", $bits(type(x)));
$display("%b", $bits(logic [0:1+$bits(type(x))]));
f(1);
void'(f(0));
t(1);
end
parameter FLAG = 1;
initial begin
logic [4:1] x = 4'b1011;
type(x ^ 3'b111) y = x ^ 3'b111;
type(x ^ 5'b11111) z = x ^ 5'b11111;
type({8 {x}}) a = {8 {x}};
type({x, y}) b = {x, y};
type(FLAG ? x : y) c = FLAG ? x : y;
type(!FLAG ? x : y) d = !FLAG ? x : y;
type($clog2(x)) e = $clog2(x);
type(!e) f = !e;
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
$display("%b %d %d", a, $left(a), $right(a));
$display("%b %d %d", b, $left(b), $right(b));
$display("%b %d %d", c, $left(c), $right(c));
$display("%b %d %d", d, $left(d), $right(d));
$display("%b %d %d", e, $left(e), $right(e));
$display("%b %d", f, $bits(f));
end
parameter W = 4;
initial begin
type('1) w = '1;
logic [W-1:0] x = 4'hA;
type(FLAG ? x : '1) y = FLAG ? x : '1;
type(!FLAG ? y : '1) z = !FLAG ? y : '1;
$display("%b %d %d", w, $left(w), $right(w));
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
end
initial begin
type(1) w = 1;
type(-1) x = -1;
type(32'hffff_ffff) y = 32'hffff_ffff;
type(32'shffff_ffff) z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, $left(w), $right(w));
$display("%b %d %d %d", x, x, $left(x), $right(x));
$display("%b %d %d %d", y, y, $left(y), $right(y));
$display("%b %d %d %d", z, z, $left(z), $right(z));
end
for (genvar i = 0; i < 2; ++i)
initial begin
type(i) a;
a = ~i;
$display("%b %d %d %d", i, i, $left(i), $right(i));
$display("%b %d %d %d", a, a, $left(a), $right(a));
end
localparam X = 5'b10110;
localparam Y = X + 6'b00001;
localparam [7:0] Z = 234;
initial begin
type(X) tX = X;
type(Y) tY = Y;
type(Z) tZ = Z;
$display("%b %d %d %d", X, X, $left(X), $right(X));
$display("%b %d %d %d", Y, Y, $left(Y), $right(Y));
$display("%b %d %d %d", Z, Z, $left(Z), $right(Z));
$display("%b %d %d %d", tX, tX, $left(tX), $right(tX));
$display("%b %d %d %d", tY, tY, $left(tY), $right(tY));
$display("%b %d %d %d", tZ, tZ, $left(tZ), $right(tZ));
end
endmodule
test/basic/typeof.v deleted 100644 → 0
module top;
function f;
input x;
begin
f = 1'b1 ^ x;
$display("f(%b) called", x);
end
endfunction
task t;
input x;
$display("t(%b) called", x);
endtask
initial begin : block
reg x, y;
x = f(0);
y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", 32'd1);
$display("%b", 32'd1);
$display("%b", 32'd3);
x = f(1);
x = f(0);
t(1);
end
parameter FLAG = 1;
initial begin : block2
reg [4:1] x;
reg [3:0] y;
reg [4:0] z;
reg [31:0] a;
reg [7:0] b;
reg [3:0] c, d;
integer e;
reg f;
x = 4'b1011;
y = x ^ 3'b111;
z = x ^ 5'b11111;
a = {8 {x}};
b = {x, y};
c = FLAG ? x : y;
d = !FLAG ? x : y;
e = $clog2(x);
f = !e;
$display("%b %d %d", x, 4, 1);
$display("%b %d %d", y, 3, 0);
$display("%b %d %d", z, 4, 0);
$display("%b %d %d", a, 31, 0);
$display("%b %d %d", b, 7, 0);
$display("%b %d %d", c, 3, 0);
$display("%b %d %d", d, 3, 0);
$display("%b %d %d", e, 31, 0);
$display("%b %d", f, 1);
end
parameter W = 4;
initial begin : block3
reg w;
reg [W-1:0] x, y, z;
w = 1;
x = 4'hA;
y = FLAG ? x : 4'hF;
z = !FLAG ? y : 4'hF;
$display("%b %d %d", w, 0, 0);
$display("%b %d %d", x, W-1, 0);
$display("%b %d %d", y, W-1, 0);
$display("%b %d %d", z, W-1, 0);
end
initial begin : block4
integer w, x, z;
reg [31:0] y;
w = 1;
x = -1;
y = 32'hffff_ffff;
z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, 31, 0);
$display("%b %d %d %d", x, x, 31, 0);
$display("%b %d %d %d", y, y, 31, 0);
$display("%b %d %d %d", z, z, 31, 0);
end
generate
genvar i;
for (i = 0; i < 2; i = i + 1)
initial begin : block5
localparam a = ~i;
$display("%b %d %d %d", i, i, 31, 0);
$display("%b %d %d %d", a, a, 31, 0);
end
endgenerate
localparam X = 5'b10110;
localparam Y = X + 6'b00001;
localparam [7:0] Z = 234;
initial begin : block5
reg [4:0] tX;
reg [5:0] tY;
reg [7:0] tZ;
tX = X;
tY = Y;
tZ = Z;
$display("%b %d %d %d", X, X, 4, 0);
$display("%b %d %d %d", Y, Y, 5, 0);
$display("%b %d %d %d", Z, Z, 7, 0);
$display("%b %d %d %d", tX, tX, 4, 0);
$display("%b %d %d %d", tY, tY, 5, 0);
$display("%b %d %d %d", tZ, tZ, 7, 0);
end
endmodule
test/basic/typeof_alias.sv deleted 100644 → 0
package P;
typedef logic [1:0][2:0] T;
endpackage
module top;
P::T w;
type(w[0]) x;
type(x[0]) y;
type(w[0][0]) z;
type(w[1:0]) a;
type(w[0][1:0]) b;
initial begin
$display("%b %b %b %b", w, x, y, z);
$display("%b %b", a, b);
end
endmodule
test/basic/typeof_alias.v deleted 100644 → 0
module top;
wire [5:0] w;
wire [2:0] x;
wire y;
wire z;
wire [5:0] a;
wire [1:0] b;
initial begin
$display("%b %b %b %b", w, x, y, z);
$display("%b %b", a, b);
end
endmodule
test/basic/typeof_port.sv deleted 100644 → 0
module Example(inp, out);
input inp;
output out;
type(inp) data;
assign data = ~inp;
assign out = data;
endmodule
test/basic/typeof_port.v deleted 100644 → 0
module Example(inp, out);
input inp;
output out;
wire data;
assign data = ~inp;
assign out = data;
endmodule
test/basic/typeof_port_tb.v deleted 100644 → 0
module top;
reg inp;
wire out;
Example e(inp, out);
initial begin
$monitor("%0d %b %b", $time, inp, out);
end
endmodule
test/basic/typeof_scope.sv deleted 100644 → 0
`define TYPEOF(x) wire [$bits(x) - 1:0]
// The `REF` sections of this test are workarounds for steveicarus/iverilog#483
module top;
genvar i;
if (1) begin : blk
for (i = 0; i < 3; i = i + 1) begin : prev
localparam V = i * 2;
localparam W = V;
wire [W:0] x;
end
for (i = 0; i < 2; i = i + 1) begin : loop
`TYPEOF(prev[i+1].x) x;
if (1) begin : a
localparam j = i - 3;
if (1) begin : b
localparam i = j + 2;
`TYPEOF(prev[i+2].x) x;
if (1) begin : c
localparam j = i - 4;
if (1) begin : d
localparam i = j + 7;
localparam z = i - 1;
`TYPEOF(prev[z].x) x;
if (1) begin : e
localparam i = 0;
`ifdef REF
localparam j = 3;
`else
localparam j = $bits(blk.loop[i].a.b.c.d.x);
`endif
wire [j-1:0] y;
end
end
end
end
end
end
end
`ifdef REF
wire [1*2:0] a;
wire [2*2:0] b;
wire [1*2:0] c;
wire [2*2:0] d;
wire [1*2:0] e;
wire [2*2:0] f;
wire [1*2:0] g;
wire [1*2:0] h;
`else
`TYPEOF(blk.loop[0].x) a;
`TYPEOF(blk.loop[1].x) b;
`TYPEOF(blk.loop[0].a.b.x) c;
`TYPEOF(blk.loop[1].a.b.x) d;
`TYPEOF(blk.loop[0].a.b.c.d.x) e;
`TYPEOF(blk.loop[1].a.b.c.d.x) f;
`TYPEOF(blk.loop[0].a.b.c.d.e.y) g;
`TYPEOF(blk.loop[1].a.b.c.d.e.y) h;
`endif
`define DUMP(x) assign x = 1; initial $display(`"x: %b (%0d bits)`", x, $bits(x));
`DUMP(a) `DUMP(b) `DUMP(c) `DUMP(d) `DUMP(e) `DUMP(f) `DUMP(g) `DUMP(h)
`DUMP(blk.loop[0].x)
`DUMP(blk.loop[1].x)
`DUMP(blk.loop[0].a.b.x)
`DUMP(blk.loop[1].a.b.x)
`DUMP(blk.loop[0].a.b.c.d.x)
`DUMP(blk.loop[1].a.b.c.d.x)
`DUMP(blk.loop[0].a.b.c.d.e.y)
`DUMP(blk.loop[1].a.b.c.d.e.y)
endmodule
test/basic/typeof_scope.v deleted 100644 → 0
`define REF 1
`include "typeof_scope.sv"
test/basic/typeof_signed.v deleted 100644 → 0
`define MAKE_PRIM(typ, size) \
reg [size-1:0] typ``_unspecified = 1; \
reg [size-1:0] typ``_unsigned = 1; \
reg signed [size-1:0] typ``_signed = 1;
module top;
wire signed x;
wire signed [1:0] y;
assign x = 0;
assign y = 2;
wire signed [1:0] z;
assign z = x % y;
wire [3:0] w;
assign w = z;
initial #1 $display("%b %b %b %b", x, y, z, w);
`MAKE_PRIM(byte, 8)
`MAKE_PRIM(shortint, 16)
`MAKE_PRIM(int, 32)
integer integer_unspecified = 1;
reg [31:0] integer_unsigned = 1;
integer integer_signed = 1;
`MAKE_PRIM(longint, 64)
`MAKE_PRIM(bit, 1)
`MAKE_PRIM(reg, 1)
`MAKE_PRIM(logic, 1)
reg signed [5:0] arr;
endmodule
test/basic/unbased_unsized_default.sv deleted 100644 → 0
module Example(inp);
input [4][5] inp;
initial #1 $display("%b", inp);
endmodule
module top;
Example e1('{default:'0});
Example e2('{default:'1});
Example e3('{default:'x});
Example e4('{default:'z});
endmodule
test/basic/unbased_unsized_default.v deleted 100644 → 0
module Example(inp);
input [19:0] inp;
initial #1 $display("%b", inp);
endmodule
module top;
Example e1({20 {1'sb0}});
Example e2({20 {1'sb1}});
Example e3({20 {1'sbx}});
Example e4({20 {1'sbz}});
endmodule
test/basic/unbound_port.sv deleted 100644 → 0
`ifndef TRAIL
`define TRAIL ,
`endif
module mod #(
parameter [23:0] KEY = "INV"
) (a, b, c);
input wire [31:0] a, b, c;
initial #1 $display("%s a=%0d b=%0d c=%0d", KEY, a, b, c);
endmodule
module top;
mod #("MA0") MA0(, , );
mod #("MA1") MA1(1, , );
mod #("MA2") MA2(1, 2, );
mod #("MA3") MA3(1, 2, 3);
mod #("MA4") MA4(1, , 3);
mod #("MA5") MA5(1, , 3);
mod #("MA6") MA6(, 2, 3);
mod #("MA7") MA7(, , 3);
mod #("MB0") MB0(, , `TRAIL);
mod #("MB1") MB1(1, , `TRAIL);
mod #("MB2") MB2(1, 2, `TRAIL);
mod #("MB3") MB3(1, 2, 3 `TRAIL);
mod #("MB4") MB4(1, , 3 `TRAIL);
mod #("MB5") MB5(1, , 3 `TRAIL);
mod #("MB6") MB6(, 2, 3 `TRAIL);
mod #("MB7") MB7(, , 3 `TRAIL);
endmodule
test/basic/unbound_port.v deleted 100644 → 0
`define TRAIL
`include "unbound_port.sv"
test/basic/union.sv deleted 100644 → 0
typedef union packed {
logic [4:0] x;
logic [4:0] y;
} A;
typedef union packed {
logic [4:0] x;
logic [0:4] y;
} B;
typedef union packed {
logic [4:0] x;
logic [1:5] y;
} C;
typedef union packed {
logic [4:0] x;
struct packed {
logic [2:0] a;
logic [1:0] b;
} y;
struct packed {
logic [1:0] a;
logic [0:2] b;
} z;
} D;
module wrap;
A a;
B b;
C c;
D d;
localparam delay = 10;
initial begin
$monitor($time, " %b %b", a.x, a.y);
a.x = 5'b01101; #delay;
a.y = 5'b11101; #delay;
$monitor($time, " %b %b", b.x, b.y);
b.x = 5'b01101; #delay;
b.y = 5'b11101; #delay;
$monitor($time, " %b %b", c.x, c.y);
c.x = 5'b01101; #delay;
c.y = 5'b11101; #delay;
$monitor($time, " %b %b {%b %b} %b {%b %b}", d.x, d.y, d.y.a, d.y.b,
d.z, d.z.a, d.z.b);
d.x = 5'b01101; #delay;
d.y = '{ a: 3'b110, b: 2'b01 }; #delay;
d.z = '{ b: 3'b110, a: 2'b01 }; #delay;
d.y.a = 3'b010; #delay;
d.y.b = 2'b10; #delay;
d.z.a = 2'b11; #delay;
d.z.b = 3'b101; #delay;
end
endmodule
test/basic/union.v deleted 100644 → 0
module wrap;
initial begin
// This was generated by running the original through VCS.
$display(" 0 01101 01101");
$display(" 10 11101 11101");
$display(" 20 01101 01101");
$display(" 30 11101 11101");
$display(" 40 01101 01101");
$display(" 50 11101 11101");
$display(" 60 01101 01101 {011 01} 01101 {01 101}");
$display(" 70 11001 11001 {110 01} 11001 {11 001}");
$display(" 80 01110 01110 {011 10} 01110 {01 110}");
$display(" 90 01010 01010 {010 10} 01010 {01 010}");
$display(" 110 11010 11010 {110 10} 11010 {11 010}");
$display(" 120 11101 11101 {111 01} 11101 {11 101}");
#130;
end
endmodule
test/basic/union_tb.v deleted 100644 → 0
module top;
wrap wrap();
endmodule
test/basic/uniop_prec.sv deleted 100644 → 0
module Example(a, b);
input logic [1:0] a;
output logic b;
assign b = !(&a);
endmodule
test/basic/uniop_prec.v deleted 100644 → 0
module Example(a, b);
input wire [1:0] a;
output wire b;
assign b = !(&a);
endmodule
test/basic/uniop_prec_tb.v deleted 100644 → 0
module top;
reg [1:0] a;
wire b;
Example example(a, b);
initial begin
$monitor("%2d %b %b", $time, a, b);
#1;
#1; a[0] = 1;
#1; a[1] = 1;
#1; a[0] = 1'sbx;
end
endmodule
test/basic/unnamed_block_shadow.sv deleted 100644 → 0
`define TEST \
reg x; \
begin \
reg [1:0] x; \
$display("%0d %b", $bits(x), x); \
end \
$display("%0d %b", $bits(x), x);
module top;
task t;
input integer unused;
`TEST
endtask
function f;
input integer unused;
`TEST
endfunction
initial t(f(0));
initial begin
`TEST
end
endmodule
test/basic/unnamed_block_shadow.v deleted 100644 → 0
module top;
initial begin : blk
integer i;
reg [1:0] y;
reg x;
for (i = 0; i < 3; i = i + 1) begin
$display("%0d %b", 2, y);
$display("%0d %b", 1, x);
end
end
endmodule
test/basic/unpacked_array_depth.sv deleted 100644 → 0
module example(
input wire [7:0] inp,
output wire [7:0] out
);
assign out = ~inp;
endmodule
module top;
reg arr1 [7:0][1:0];
reg arr2 [7:0][1:0][1:0];
wire [7:0] out1, out2;
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
end
endmodule
test/basic/unpacked_array_depth.v deleted 100644 → 0
module example(
input wire [7:0] inp,
output wire [7:0] out
);
assign out = ~inp;
endmodule
module top;
reg [7:0] arr1 [1:0];
reg [7:0] arr2 [1:0][1:0];
wire [7:0] out1, out2;
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
end
endmodule
test/basic/unpacked_localparam.sv deleted 100644 → 0
module top;
localparam logic [7:0] init_val [4] = {8'd0, 8'd8, 8'd10, 8'd200};
initial begin
integer i, j;
for (i = 0; i < 4; i += 1) begin
$display(init_val[i]);
for (j = 0; j < 8; j += 1) begin
$display(init_val[i][j]);
end
end
end
endmodule
test/basic/unpacked_localparam.v deleted 100644 → 0
module top;
localparam [31:0] init_val = {8'd0, 8'd8, 8'd10, 8'd200};
initial begin : foo
integer i, j;
for (i = 3; i >= 0; i -= 1) begin
$display(init_val[8*i+:8]);
for (j = 0; j < 8; j += 1) begin
$display(init_val[8*i+j]);
end
end
end
endmodule
test/basic/unsigned.sv deleted 100644 → 0
module top;
logic [3:0] arr;
initial
for (int unsigned i = 0; i < 4; i++)
arr[i] = i;
initial $display(arr);
parameter unsigned foo = 1;
localparam unsigned bar = 1;
initial $display(foo, bar);
endmodule
test/basic/unsigned.v deleted 100644 → 0
module top;
reg [3:0] arr;
initial begin : block_name
integer i;
for (i = 0; i < 4; i++)
arr[i] = i;
end
initial $display(arr);
parameter foo = 1;
localparam bar = 1;
initial $display(foo, bar);
endmodule
test/basic/unused_imports.sv deleted 100644 → 0
package P;
localparam FOO = 1;
localparam BAR = 2;
endpackage
import P::*;
module top;
initial $display(FOO);
endmodule
test/basic/unused_imports.v deleted 100644 → 0
module top;
localparam FOO = 1;
initial $display(FOO);
endmodule
test/basic/wire_reg.sv deleted 100644 → 0
module top(inp, out);
input wire inp;
reg data;
always @* data = inp;
output logic [1:0] out;
parameter ON = 1;
generate
if (ON) begin : blk
assign out[0] = data;
always @* out[1] = data;
end
endgenerate
endmodule
test/basic/wire_reg.v deleted 100644 → 0
module top(inp, out);
input wire inp;
reg data;
always @* data = inp;
output reg [1:0] out;
parameter ON = 1;
generate
if (ON) begin : blk
always @* out[0] = data;
always @* out[1] = data;
end
endgenerate
endmodule
test/core/package_enum_1.v 0 → 100644
module top;
wire [2:0] test;
assign test = 3'd0;
initial $display(test);
endmodule
test/core/package_enum_3.sv 0 → 100644
package foo_pkg;
typedef enum logic [2:0] {
AccessAck = 3'd0,
AccessAckData = 3'd1
} inp_t;
endpackage
module top;
import foo_pkg::*;
wire [2:0] test;
always_comb begin
case (test)
AccessAck: $display("Ack");
default : $display("default");
endcase
end
endmodule
test/core/package_export_nothing.v 0 → 100644
module top;
localparam Bar = 2;
initial $display(Bar);
endmodule
test/core/package_export_wildcard.sv 0 → 100644
package P;
localparam X = 1;
endpackage
package Q;
import P::X;
export P::*;
localparam Y = 2;
endpackage
package R;
import Q::X;
export Q::*;
localparam Z = 3;
endpackage
package S;
import P::X;
import Q::Y;
import R::Z;
export *::*;
endpackage
module top;
import S::*;
initial $display(X, Y, Z);
endmodule
test/core/package_export_wildcard.v 0 → 100644
module top;
localparam X = 1;
localparam Y = 2;
localparam Z = 3;
initial $display(X, Y, Z);
endmodule
test/core/package_function_cast.sv 0 → 100644
package P;
function automatic logic [7:0] f(input logic [2:0] p);
logic [7:0] r;
localparam T = $bits(r[7:0]);
r = T'(1'sb0);
r[p+:2] = $bits(r[p+:2])'(1'sb1);
return r;
endfunction
endpackage
module top;
logic [2:0] p;
logic [7:0] q;
assign q = P::f(p);
initial begin
$monitor("%0d, p=%b q=%b", $time, p, q);
#1 p = 0;
while (p != 7)
#1 p = p + 1;
end
endmodule
test/core/package_function_cast.v 0 → 100644
module top;
function automatic [7:0] f;
input [2:0] p;
begin
f = 7'b0;
f[p+:2] = 2'b11;
end
endfunction
reg [2:0] p;
wire [7:0] q;
assign q = f(p);
initial begin
$monitor("%0d, p=%b q=%b", $time, p, q);
#1 p = 0;
while (p != 7)
#1 p = p + 1;
end
endmodule
test/basic/package_export_wildcard.v → test/core/package_global.sv
module top; package PkgA;
localparam X = 1; localparam X = 1;
localparam Y = 2; localparam Y = 2;
localparam Z = 3; endpackage
package PkgB;
localparam X = 3;
localparam Z = 4;
endpackage
import PkgA::*;
import PkgB::*;
localparam X = 5;
module top;
initial $display(X, Y, Z); initial $display(X, Y, Z);
endmodule endmodule
test/core/package_global.v 0 → 100644
module top;
localparam X = 5;
localparam Y = 2;
localparam Z = 4;
initial $display(X, Y, Z);
endmodule
test/core/package_implied.v 0 → 100644
module top;
localparam P_X = 10;
localparam Y = P_X;
initial $display(Y);
endmodule
test/core/package_order.sv 0 → 100644
package evil_pkg;
localparam Z = 1;
localparam A = Z;
localparam B = Z;
function logic evil_fun;
return A;
endfunction
endpackage
module evil_mdl (
output logic [evil_pkg::B-1:0] foo
);
initial foo = evil_pkg::evil_fun();
endmodule
module top;
logic [evil_pkg::B-1:0] foo;
evil_mdl x(foo);
initial $monitor(foo);
endmodule
test/core/package_order.v 0 → 100644
module evil_mdl (
output reg [evil_pkg_B-1:0] foo
);
localparam evil_pkg_Z = 1;
localparam evil_pkg_A = evil_pkg_Z;
localparam evil_pkg_B = evil_pkg_Z;
initial foo = evil_pkg_A;
endmodule
module top;
localparam evil_pkg_Z = 1;
localparam evil_pkg_A = evil_pkg_Z;
localparam evil_pkg_B = evil_pkg_Z;
wire [evil_pkg_B-1:0] foo;
evil_mdl x(foo);
initial $monitor(foo);
endmodule
test/core/package_param_tb.v 0 → 100644
module top;
Example e1();
Example #(8) e2();
Example #(9) e3();
endmodule
test/core/package_pattern.sv 0 → 100644
package PKG;
typedef struct packed {
logic f;
} foo_t;
endpackage
module top;
typedef struct packed {
PKG::foo_t f;
} local_t;
local_t w[0:1];
initial begin
w <= '{default: 0};
$display("%b", w);
end
endmodule
test/core/package_pattern.v 0 → 100644
module top;
reg [1:0] w;
initial begin
w <= 2'b00;
$display("%b", w);
end
endmodule
test/core/package_scope.v 0 → 100644
module top;
initial begin
$display("A 3");
$display("B 3");
$display("C 1");
$display("D 2");
$display("E 2");
$display("F 2");
// G doesn't print
$display("H 1");
$display("I 1");
$display("J 1");
$display("K1 1");
$display("K2 2");
$display("K3 3");
$display("K4 2");
$display("K0 1");
$display("L 1");
$display("M1 1");
$display("M2 1");
$display("M3 1");
$display("M4 1");
$display("W::help() 1");
$display("W::help() 1");
$display("N1 1");
$display("N2 2");
$display("O1 1");
$display("O2 2");
end
endmodule
test/core/package_self_reference.v 0 → 100644
module top;
localparam Foo = 1;
initial $display(Foo);
endmodule
test/core/package_self_reference_import.sv 0 → 100644
package Q;
localparam Bar = 1;
endpackage
package P;
import Q::Bar;
localparam Foo = P::Bar;
endpackage
module top;
import P::*;
initial $display(Foo);
endmodule
test/core/package_self_reference_import.v 0 → 100644
module top;
localparam Foo = 1;
initial $display(Foo);
endmodule
test/core/package_self_reference_shadow.sv 0 → 100644
package P;
localparam Bar = 1;
function automatic integer func;
localparam Bar = 2;
func = Bar + P::Bar;
endfunction
endpackage
module top;
import P::*;
initial $display(func());
endmodule
test/core/package_self_reference_shadow.v 0 → 100644
module top;
localparam Foo = 1;
localparam Bar = 2;
initial $display(Foo + Bar);
endmodule
test/core/package_shadow.sv 0 → 100644
package P;
localparam X = 10;
localparam Y = X + 1;
function integer flip;
input integer X;
return ~X;
endfunction
endpackage
package Q;
import P::*;
localparam Y = X + 1000;
endpackage
package R;
import Q::*;
export Q::Y;
endpackage
package S;
typedef enum logic { A, B } enum_t;
function enum_t flop;
input enum_t X;
if (X == A) return B;
else return A;
endfunction
endpackage
module top;
import P::*;
localparam X = 20;
localparam Z = Y + 1;
import S::flop;
typedef enum logic [3:0] { T = 3, U } enum_t;
initial begin
$display("X %0d", X);
$display("P::Y %0d", P::Y);
$display("Z %0d", Z);
$display("R::Y %0d", R::Y);
$display("flip(0) %0d", flip(0));
$display("T %b", T);
$display("U %b", U);
$display("flop(0) %b", flop(0));
$display("flop(1) %b", flop(1));
end
endmodule
test/core/package_shadow.v 0 → 100644
module top;
localparam P_X = 10;
localparam P_Y = P_X + 1;
localparam X = 20;
localparam Z = P_Y + 1;
localparam R_Y = P_X + 1000;
localparam Q_Y = R_Y;
localparam [3:0] T = 3;
localparam [3:0] U = 4;
function integer flip;
input integer inp;
flip = ~inp;
endfunction
function flop;
input inp;
flop = ~inp;
endfunction
initial begin
$display("X %0d", X);
$display("P::Y %0d", P_Y);
$display("Z %0d", Z);
$display("R::Y %0d", Q_Y);
$display("flip(0) %0d", flip(0));
$display("T %b", T);
$display("U %b", U);
$display("flop(0) %b", flop(0));
$display("flop(1) %b", flop(1));
end
endmodule
test/core/package_typedef.sv 0 → 100644
package top_pkg;
localparam AW = 16;
endpackage
package foo_pkg;
typedef struct packed {
logic valid;
logic value;
} mask_t;
typedef struct packed {
logic valid;
logic [top_pkg::AW-1:0] user;
mask_t mask;
} boo_t;
endpackage
module top;
foo_pkg::boo_t foo;
assign foo = 19'b110_01001000_01110100;
wire [7:0] bar;
parameter FLAG = 1;
assign bar = FLAG ? foo.user[0+:8] : '1;
endmodule
test/core/package_typedef.v 0 → 100644
module top;
localparam AW = 16;
wire [AW+2:0] foo;
assign foo = 19'b110_01001000_01110100;
wire [7:0] bar;
parameter FLAG = 1;
assign bar = FLAG ? foo[2+:8] : 8'hFF;
endmodule
test/core/package_typedef_nested.sv 0 → 100644
package foo_pkg;
typedef struct packed {
logic [7:0] rsvd;
logic [7:0] parity;
} user_t;
typedef struct packed {
logic valid;
user_t user;
} inp_t;
typedef struct packed {
logic valid;
logic opcode;
} out_t;
endpackage
module top (
input foo_pkg::inp_t dat_i,
output foo_pkg::out_t dat_o
);
endmodule
test/core/package_typedef_nested.v 0 → 100644
module top (dat_i, dat_o);
input wire [16:0] dat_i;
output wire [1:0] dat_o;
endmodule
test/core/packed_array.sv 0 → 100644
module top;
logic [2:0][3:0] arr [1:0];
initial begin
for (int i = 0; i <= 1; i++) begin
for (int j = 0; j <= 2; j++) begin
for (int k = 0; k <= 3; k++) begin
$display("%b", arr[i][j][k]);
arr[i][j][k] = 1'(i+j+k);
$display("%b", arr[i][j][k]);
end
end
end
end
endmodule
test/core/packed_array.v 0 → 100644
module top;
reg arr [1:0][2:0][3:0];
initial begin : block_name
integer i, j, k;
for (i = 0; i <= 1; i++) begin
for (j = 0; j <= 2; j++) begin
for (k = 0; k <= 3; k++) begin
$display("%b", arr[i][j][k]);
arr[i][j][k] = i+j+k;
$display("%b", arr[i][j][k]);
end
end
end
end
endmodule
test/core/param_shorthand.sv 0 → 100644
module top #(FOO = 10);
initial $display(FOO);
endmodule
module top2 #(FOO = 10, BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(FOO = 10, BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule
test/core/param_shorthand.v 0 → 100644
module top #(parameter FOO = 10);
initial $display(FOO);
endmodule
module top2 #(parameter FOO = 10, parameter BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(parameter FOO = 10, parameter BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule
test/core/parameterized_data_types.sv 0 → 100644
class P #(
parameter WIDTH = 1,
parameter type BASE = logic
);
typedef BASE [WIDTH - 1:0] Unit;
endclass
`define DUMP \
begin \
a = '1; \
b = '1; \
c = '1; \
d = '1; \
e = '1; \
$display("%b %b %b %b %b", a, b, c, d, e); \
end
module top;
localparam X = 2;
localparam type T = logic [31:0];
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
initial `DUMP
if (1) begin : blk
localparam X = 3;
localparam type T = logic [7:0];
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
initial `DUMP
end
if (1) begin : route
localparam X = 3;
localparam type T = logic [7:0];
initial begin
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
begin
P#()::Unit a;
P#(X)::Unit b;
P#(X, T)::Unit c;
P#(.WIDTH(X))::Unit d;
P#(.BASE(T))::Unit e;
`DUMP
end
end
end
endmodule
test/core/parameterized_data_types.v 0 → 100644
`define DUMP \
begin \
a = 1'sb1; \
b = 1'sb1; \
c = 1'sb1; \
d = 1'sb1; \
e = 1'sb1; \
$display("%b %b %b %b %b", a, b, c, d, e); \
end
module top;
reg [0:0] a;
reg [1:0] b;
reg [63:0] c;
reg [1:0] d;
reg [31:0] e;
initial `DUMP
generate
if (1) begin : blk
reg [0:0] a;
reg [2:0] b;
reg [23:0] c;
reg [2:0] d;
reg [7:0] e;
initial
repeat (4)
`DUMP
end
endgenerate
endmodule
test/core/paramtype_bits.sv 0 → 100644
module Module(out);
parameter type T = logic;
output T out;
assign out = '1;
endmodule
module top;
logic w;
logic [$bits(w)-1:0] b;
logic o0, o1;
logic [1:0] o2;
Module m0(o0);
Module #(logic[$bits(w)-1:0]) m1(o1);
Module #(logic[$bits(b)*2-1:0]) m2(o2);
endmodule
test/core/paramtype_bits.v 0 → 100644
module Module_Size1(out);
output wire out;
assign out = 1'b1;
endmodule
module Module_Size2(out);
output wire [1:0] out;
assign out = 2'b11;
endmodule
module top;
wire w;
wire [0:0] b;
wire o0, o1;
wire [1:0] o2;
Module_Size1 m0(o0);
Module_Size1 m1(o1);
Module_Size2 m2(o2);
endmodule
test/core/paramtype_delay.sv 0 → 100644
module mod #(
parameter STR = "",
parameter type T = logic,
parameter WIDTH = 32,
parameter type WIDTH_T = logic [WIDTH-1:0],
parameter T INDIRECT = 0,
parameter type OTHER_T = struct packed { type(INDIRECT) x, y; }
);
initial begin
$display("%s $bits(T) = %0d", STR, $bits(T));
$display("%s WIDTH = %0d", STR, WIDTH);
$display("%s $bits(WIDTH_T) = %0d", STR, $bits(WIDTH_T));
$display("%s $bits(OTHER_T) = %0d", STR, $bits(OTHER_T));
end
endmodule
module top;
parameter type BASE = byte;
typedef struct packed { BASE y; } W;
W w;
typedef struct packed { type(w) x, y; } V;
V v;
typedef logic [$bits(v)*2-1:0] U;
U u;
`define TEST(x) \
assign x = 0; \
mod #(`"x`", type(x)) m``x();
`TEST(w)
`TEST(v)
`TEST(u)
mod #("t") mt();
endmodule
test/core/paramtype_delay.v 0 → 100644
module mod #(
parameter STR = "",
parameter T = 1
);
initial begin
$display("%s $bits(T) = %0d", STR, T);
$display("%s WIDTH = %0d", STR, 32);
$display("%s $bits(WIDTH_T) = %0d", STR, 32);
$display("%s $bits(OTHER_T) = %0d", STR, 2 * T);
end
endmodule
module top;
`define TEST(x, w) \
wire [w-1:0] x; \
assign x = 0; \
mod #(`"x`", w) m``x();
`TEST(w, 8)
`TEST(v, 16)
`TEST(u, 32)
mod #("t") mt();
endmodule
test/core/paramtype_expr.sv 0 → 100644
module mod #(
parameter type T = logic
);
initial $display("$bits(T) = %0d", $bits(T));
endmodule
module top;
parameter SIZE = 8;
mod #(logic [SIZE-1:0]) m();
endmodule
test/core/paramtype_expr.v 0 → 100644
module mod #(
parameter S = 1
);
initial $display("$bits(T) = %0d", S);
endmodule
module top;
parameter SIZE = 8;
mod #(SIZE) m();
endmodule
test/core/paramtype_hier.sv 0 → 100644
module Module #(
parameter int S,
parameter type T
);
T x;
if (S) begin : a
if (S) begin : b
assign Module.x = '1;
logic [$bits(Module.x):0] y = 'z;
end
end
initial $display("Module %0d: %b %0d %b %0d", S, Module.x, $bits(T), Module.a.b.y, $bits(Module.a.b.y));
endmodule
module top;
parameter ONE = 1;
logic [ONE*7:ONE*0] x;
if (1) begin : blk
localparam W = ONE * 3;
typedef logic [W-1:$bits(x)] T;
T x;
end
Module #(1, logic [$bits(x)-1:0]) m1();
Module #(2, logic [$bits(blk.x)-1:0]) m2();
Module #(3, logic [top.blk.W-1:0]) m3();
endmodule
test/core/paramtype_hier.v 0 → 100644
module Module;
parameter S = 0;
parameter T = 0;
wire [T-1:0] x;
generate
if (S) begin : a
if (S) begin : b
assign Module.x = 1'sb1;
wire [T:0] y = 1'sbz;
end
end
endgenerate
initial $display("Module %0d: %b %0d %b %0d", S, Module.x, T, Module.a.b.y, T + 1);
endmodule
module top;
parameter ONE = 1;
wire [ONE*7:ONE*0] x;
if (1) begin : blk
localparam W = ONE * 3;
wire [W-1:$bits(x)] x;
end
Module #(1, 8) m1();
Module #(2, 7) m2();
Module #(3, 3) m3();
endmodule
test/core/paramtype_param.sv 0 → 100644
package PKG;
typedef struct packed {
int W;
} F_t;
localparam F_t F_v = '{
W: 64
};
endpackage
module M0 #(
parameter type T,
parameter ID = "NONE"
);
T v;
initial $display("%s %0d %0d", ID, $bits(T), $bits(v));
endmodule
module M1 #(parameter PKG::F_t F = PKG::F_v) ();
typedef struct packed {
logic [F.W-1:0] field;
} local_t;
local_t v;
M0 #(.ID("A"), .T(local_t)) a();
M0 #(.ID("B"), .T(PKG::F_t)) b();
endmodule
module top;
typedef struct packed {
byte W;
} F_t;
localparam F_t F = '{
W: 16
};
typedef struct packed {
logic [F.W-1:0] field;
} local_t;
local_t v;
M1 m1();
M0 #(.ID("C"), .T(local_t)) c();
M0 #(.ID("D"), .T(PKG::F_t)) d();
M0 #(.ID("E"), .T(F_t)) e();
endmodule
test/core/paramtype_param.v 0 → 100644
module top;
localparam FORMAT = "%s %0d %0d";
initial begin
$display(FORMAT, "A", 64, 64);
$display(FORMAT, "B", 32, 32);
$display(FORMAT, "C", 16, 16);
$display(FORMAT, "D", 32, 32);
$display(FORMAT, "E", 8, 8);
end
endmodule
test/core/paramtype_param_default.sv 0 → 100644
module M #(
parameter ID = "Z",
parameter K = 2,
parameter type T = logic [K-1:0]
);
initial $display("%s %0d %0d", ID, K, $bits(T));
endmodule
module top;
M z();
M #(.ID("A")) a();
M #(.ID("B"), .K(3)) b();
M #(.ID("C"), .K(4)) c();
parameter K = 4;
localparam type T = logic [2*K-1:0];
M #(.ID("D"), .K(4), .T(T)) d();
endmodule
test/core/paramtype_param_default.v 0 → 100644
module M #(
parameter ID = "Z",
parameter K = 2,
parameter T = K
);
initial $display("%s %0d %0d", ID, K, T);
endmodule
module top;
M z();
M #(.ID("A")) a();
M #(.ID("B"), .K(3)) b();
M #(.ID("C"), .K(4)) c();
M #(.ID("D"), .K(4), .T(8)) d();
endmodule
test/core/paramtype_recurse.sv 0 → 100644
module foo #(
parameter type T = logic,
parameter size = 0
);
generate
if (size != 0) begin : foo
bar #(T, size - 1) x();
end
endgenerate
initial $display("foo %d %d", $bits(T), size);
endmodule
module bar #(
parameter type U = logic,
parameter size = 0
);
generate
if (size != 0) begin : bar
foo #(U, size - 1) x();
end
endgenerate
initial $display("bar %d %d", $bits(U), size);
endmodule
module top_1; foo #(byte, 2) x(); endmodule
module top_2; bar #(byte, 3) x(); endmodule
module top_3; foo #(bit, 4) x(); endmodule
module top_4; bar #(bit, 5) x(); endmodule
module top; foo x(); endmodule
test/core/paramtype_recurse.v 0 → 100644
module foo_byte #(
parameter size = 0
);
generate
if (size != 0) begin : foo
bar_byte #(size - 1) x();
end
endgenerate
initial $display("foo %d %d", 8, size);
endmodule
module bar_byte #(
parameter size = 0
);
generate
if (size != 0) begin : bar
foo_byte #(size - 1) x();
end
endgenerate
initial $display("bar %d %d", 8, size);
endmodule
module foo_bit #(
parameter size = 0
);
generate
if (size != 0) begin : foo
bar_bit #(size - 1) x();
end
endgenerate
initial $display("foo %d %d", 1, size);
endmodule
module bar_bit #(
parameter size = 0
);
generate
if (size != 0) begin : bar
foo_bit #(size - 1) x();
end
endgenerate
initial $display("bar %d %d", 1, size);
endmodule
module top_1; foo_byte #(2) x(); endmodule
module top_2; bar_byte #(3) x(); endmodule
module top_3; foo_bit #(4) x(); endmodule
module top_4; bar_bit #(5) x(); endmodule
module top; foo_bit #(0) x(); endmodule
test/core/paramtype_struct_default.sv 0 → 100644
module example(inp, data, valid);
parameter W = 16;
typedef struct packed {
logic [W-1:0] data;
logic valid;
} line_t;
parameter type local_line_t = line_t;
input local_line_t inp;
output logic [W-1:0] data;
assign data = inp.data;
output logic valid;
assign valid = inp.valid;
endmodule
module top;
reg [16:0] inp;
wire [15:0] data;
wire valid;
example e(.*);
initial inp = 17'b1_01100011_11001111;
endmodule
test/core/paramtype_struct_default.v 0 → 100644
module top;
reg [16:0] inp;
wire [15:0] data;
wire valid;
assign data = inp[16:1];
assign valid = inp[0];
initial inp = 17'b1_01100011_11001111;
endmodule
test/core/part_select.sv 0 → 100644
module top;
wire [31:0] a;
wire [0:31] b;
assign a = 'h64ded943, b = 'hb7151d17;
initial begin
$display(a[0+:8]);
$display(a[15-:8]);
$display(b[0+:8]);
$display(b[15-:8]);
end
endmodule
test/core/part_select.v 0 → 100644
module top;
wire [31:0] a;
wire [0:31] b;
assign a = 'h64ded943, b = 'hb7151d17;
initial begin
$display(a[7:0]);
$display(a[15:8]);
$display(b[0:7]);
$display(b[8:15]);
end
endmodule
test/core/part_select_bits.sv 0 → 100644
module top;
parameter A = 3;
parameter B = 4;
logic [A*B-1:0] arr;
initial begin
arr = 0;
for (integer i = 0; i < A; ++i) begin
// yes this is silly but it captures an interesting edge case
arr[i * B +: B] = $bits(arr[i * B +: B])'(i);
end
$display("%b", arr);
end
endmodule
test/core/part_select_bits.v 0 → 100644
module top;
parameter A = 3;
parameter B = 4;
reg [A*B-1:0] arr;
initial begin : foo
integer i;
arr = 0;
for (i = 0; i < A; ++i) begin
arr[i * B +: B] = i;
end
$display("%b", arr);
end
endmodule
test/core/pattern.sv 0 → 100644
module test;
typedef struct packed {
int w, x;
byte y;
logic z;
} struct_a;
struct_a a;
initial begin
$monitor("%2d: %b %b %b %b %b", $time, a, a.w, a.x, a.y, a.z);
#1 a.w = 0;
#1 a.x = 0;
#1 a.y = 0;
#1 a.z = 0;
#1 a = '{default: 1};
#1 a = '{default: 2};
#1 a = '{default: 3};
#1 a = '{default: 0};
#1 a = '{default: -1};
#1 a = '{default: -2};
#1 a = '{int: 0, default: 1};
#1 a = '{byte: 0, default: 1};
#1 a = '{logic: 0, default: 1};
#1 a = '{logic: 1, int: 2, byte: 3};
#1 a = '{logic: 1, int: 2, byte: 3, default: -1};
#1 a = '{int: 3, byte: 2, default: 0};
#1 a = '{w: 8, int: 0, default: 1};
#1 a = '{w: 8, byte: 0, default: 1};
#1 a = '{w: 8, logic: 0, default: 1};
#1 a = '{w: 8, logic: 1, int: 2, byte: 3};
#1 a = '{w: 8, logic: 1, int: 2, byte: 3, default: -1};
#1 a = '{w: 8, int: 3, byte: 2, default: 0};
end
typedef struct packed {
int x;
struct_a y;
logic z;
} struct_b;
struct_b b;
initial begin
#100;
$monitor("%2d: %b %b %b %b", $time, b, b.x, b.y, b.z);
#1 b.x = 0;
#1 b.y = 0;
#1 b.z = 0;
#1 b = '{default: 1};
#1 b = '{default: 2};
#1 b = '{default: 3};
#1 b = '{default: 0};
#1 b = '{default: -1};
#1 b = '{default: -2};
#1 b = '{int: 0, default: 1};
#1 b = '{byte: 0, default: 1};
#1 b = '{logic: 0, default: 1};
#1 b = '{logic: 1, int: 2, byte: 3};
#1 b = '{logic: 1, int: 2, byte: 3, default: -1};
#1 b = '{int: 3, byte: 2, default: 0};
end
endmodule
module top; endmodule
test/core/pattern_revised.sv 0 → 100644
module top;
parameter PARAM = 1;
`define BASE(expr, full, x, y, z) \
$display(`"%b %0d %0d %0d expr`", \
full, x, y, z)
`ifndef TEST
typedef byte T;
typedef struct packed {
byte x;
T y;
integer z;
} S;
`define TEST(a, b, c, expr) \
if (PARAM) begin \
S s; \
assign s = expr; \
initial `BASE(expr, s, s.x, s.y, s.z); \
end
`endif
`TEST(1, 2, 3, '{ x: 1, y: 2, z: 3 })
`TEST(2, 2, 3, '{ byte: 2, integer: 3 })
`TEST(3, 3, 2, '{ integer: 2, byte: 3 })
`TEST(4, 4, 2, '{ integer: 2, T: 4 })
`TEST(5, 5, 2, '{ integer: 2, T: 4, byte: 5 })
`TEST(5, 5, 2, '{ 2: 2, byte: 5 })
`TEST(7, 8, 9, '{ 1: 8, 2: 9, 0: 7 })
endmodule
test/core/pattern_revised.v 0 → 100644
`define TEST(aVal, bVal, cVal, expr) \
if (PARAM) begin \
wire [7:0] a, b; \
wire [31:0] c; \
assign a = aVal; \
assign b = bVal; \
assign c = cVal; \
initial `BASE(expr, {a, b, c}, a, b, c); \
end
`include "pattern_revised.sv"
test/core/port_typename.sv 0 → 100644
typedef wire b_t;
module top(
input a [1:0],
input b_t b
);
initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
endmodule
test/core/port_typename.v 0 → 100644
module top(
input [1:0] a,
input wire b
);
initial $display("%d %d %1d %1d", a, b, $bits(a), $bits(b));
endmodule
test/core/reorder.sv 0 → 100644
module top;
assign arr[0][0] = 1;
logic [1:0][2:0] arr;
initial $display("%b", arr);
parameter YES = 1;
if (YES) begin : blk
assign brr[0][0] = 1;
logic [2:0][3:0] brr;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0][0] = 1;
logic [3:0][4:0] crr;
initial $display("%b", crr);
end
end
endmodule
test/core/reorder.v 0 → 100644
module top;
wire [5:0] arr;
assign arr[0] = 1;
initial $display("%b", arr);
parameter YES = 1;
generate
if (YES) begin : blk
wire [11:0] brr;
assign brr[0] = 1;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0] = 1;
wire [19:0] crr;
initial $display("%b", crr);
end
end
endgenerate
endmodule
test/core/run.sh 0 → 100755
#!/bin/bash
source ../lib/runner.sh
test/core/shadow_recurse.sv 0 → 100644
module top;
initial begin
logic x;
$display($bits(x));
begin
logic [0:$bits(x)] x;
$display($bits(x));
begin
logic [0:$bits(x)] x;
$display($bits(x));
end
end
end
initial begin
logic x;
$display($bits(type(x)));
begin
logic [0:$bits(type(x))] x;
$display($bits(type(x)));
begin
logic [0:$bits(type(x))] x;
$display($bits(type(x)));
end
end
end
initial begin
logic x;
$display($bits(x));
begin
logic [0:$bits(type(x))] x;
$display($bits(x));
begin
logic [0:$bits(type(x))] x;
$display($bits(x));
end
end
end
initial begin
logic x;
$display($bits(type(x)));
begin
logic [0:$bits(x)] x;
$display($bits(type(x)));
begin
logic [0:$bits(x)] x;
$display($bits(type(x)));
end
end
end
endmodule
test/core/shadow_recurse.v 0 → 100644
module top;
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
initial begin
$display(1);
$display(2);
$display(3);
end
endmodule
test/core/sign_cast.sv 0 → 100644
module top;
initial begin
$display(signed'(4294967295));
$display(unsigned'(4294967295));
$display(signed'(-1));
$display(unsigned'(-1));
end
endmodule
test/core/sign_cast.v 0 → 100644
module top;
initial begin
$display($signed(4294967295));
$display($unsigned(4294967295));
$display($signed(-1));
$display($unsigned(-1));
end
endmodule
test/core/simple_loop_jump.sv 0 → 100644
module top;
function automatic integer f;
input integer inp;
f = 1;
for (integer idx = 0; idx < inp; idx = idx + 1) begin
if (f == 32)
break;
f = f * 2;
end
endfunction
function automatic integer g;
input integer inp;
integer idx;
g = 1;
for (idx = 0; idx < inp; idx = idx + 1) begin
if (g == 32)
break;
g = g * 2;
end
g += idx;
endfunction
function automatic integer h;
input integer inp;
integer idx;
h = 1;
for (idx = 0; idx + 1 < 1 + inp; idx = idx + 1) begin
if (h == 32)
break;
h = h * 2;
end
h += idx + 1;
endfunction
function automatic integer j;
input integer inp;
for (j = 0; j < inp; j = j + 1)
if (j == 3)
return j;
j *= 2;
endfunction
function automatic integer k;
input integer inp;
for (k = 0; k + 1 < 1 + inp; k = k + 1)
if (k == 3)
return k * 3;
k = k * 2 + 1;
endfunction
integer i;
initial
for (i = 0; i < 10; i = i + 1) begin
$display("f(%0d) = %0d", i, f(i));
$display("g(%0d) = %0d", i, g(i));
$display("h(%0d) = %0d", i, h(i));
$display("j(%0d) = %0d", i, j(i));
$display("k(%0d) = %0d", i, k(i));
end
endmodule
test/core/simple_loop_jump.v 0 → 100644
module top;
function automatic integer f;
input integer inp;
if (inp > 5)
f = 32;
else
f = 2 ** inp;
endfunction
function automatic integer g;
input integer inp;
if (inp > 5)
g = 32 + 5;
else
g = 2 ** inp + inp;
endfunction
function automatic integer h;
input integer inp;
if (inp > 5)
h = 32 + 5 + 1;
else
h = 2 ** inp + inp + 1;
endfunction
function automatic integer j;
input integer inp;
if (inp > 3)
j = 3;
else
j = inp * 2;
endfunction
function automatic integer k;
input integer inp;
if (inp > 3)
k = 3 * 3;
else
k = inp * 2 + 1;
endfunction
integer i;
initial
for (i = 0; i < 10; i = i + 1) begin
$display("f(%0d) = %0d", i, f(i));
$display("g(%0d) = %0d", i, g(i));
$display("h(%0d) = %0d", i, h(i));
$display("j(%0d) = %0d", i, j(i));
$display("k(%0d) = %0d", i, k(i));
end
endmodule
test/core/simplify_func.sv 0 → 100644
package PKG;
typedef struct packed {
int F;
} S;
function automatic S f();
return '0;
endfunction
endpackage
module top;
localparam PKG::S L0 = PKG::f();
localparam int L1 = L0.F;
localparam int L2 = $clog2(L1);
initial $display("%b %b %b", L0, L1, L2);
endmodule
test/core/simplify_func.v 0 → 100644
module top;
localparam L0 = 0;
localparam L1 = L0;
localparam L2 = $clog2(L1);
initial $display("%b %b %b", L0, L1, L2);
endmodule
test/core/size_cast.sv 0 → 100644
module top;
localparam BW = 3;
logic [2:0] test;
logic [3:0] foo;
logic [3:0] bar;
integer x;
reg [7:0] y;
initial begin
test = BW'(0);
$display(test);
foo = 2'('1);
$display(foo);
bar = $bits(bar)'('1);
$display(bar);
x = 1'('1); $display("%b %0d", x, x);
y = 1'('1); $display("%b %0d", y, y);
x = 2'('0); $display("%b %0d", x, x);
y = 2'('0); $display("%b %0d", y, y);
x = 2'('1); $display("%b %0d", x, x);
y = 2'('1); $display("%b %0d", y, y);
x = 2'('x); $display("%b %0d", x, x);
y = 2'('x); $display("%b %0d", y, y);
x = 2'('z); $display("%b %0d", x, x);
y = 2'('z); $display("%b %0d", y, y);
end
endmodule
test/core/size_cast.v 0 → 100644
module top;
reg [2:0] test;
reg [3:0] foo;
reg [3:0] bar;
integer x;
reg [7:0] y;
initial begin
test = 0;
$display(test);
foo = 4'b0011;
$display(foo);
bar = 4'b1111;
$display(bar);
x = 1'b1; $display("%b %0d", x, x);
y = 1'b1; $display("%b %0d", y, y);
x = 2'b00; $display("%b %0d", x, x);
y = 2'b00; $display("%b %0d", y, y);
x = 2'b11; $display("%b %0d", x, x);
y = 2'b11; $display("%b %0d", y, y);
x = 2'bxx; $display("%b %0d", x, x);
y = 2'bxx; $display("%b %0d", y, y);
x = 2'bzz; $display("%b %0d", x, x);
y = 2'bzz; $display("%b %0d", y, y);
end
endmodule
test/core/stream.sv 0 → 100644
module top;
// Derived from: https://www.amiq.com/consulting/2017/05/29/how-to-pack-data-using-systemverilog-streaming-operators/
typedef struct packed {
logic [3:0] addr;
logic [3:0] data;
} packet_t;
initial begin
logic [1:0] array[] = '{ 2'b10, 2'b01, 2'b11, 2'b00 };
packet_t packet = {<<4{ {<<2{array}} }};
$display("packet addr = %b", packet.addr);
$display("packet data = %b", packet.data);
end
initial begin
logic [23:0] temp;
temp = {>>byte{24'h060708}};
$display("%h", temp);
temp = {<<byte{24'h060708}};
$display("%h", temp);
temp = {>>bit{24'h060708}};
$display("%h", temp);
temp = {<<bit{24'h060708}};
$display("%h", temp);
temp = {>>7{24'h060708}};
$display("%h", temp);
temp = {<<7{24'h060708}};
$display("%h", temp);
temp = {>>7{20'h60708}};
$display("%h", temp);
temp = {<<7{20'h60708}};
$display("%h", temp);
temp = {>>7{16'h0708}};
$display("%h", temp);
temp = {<<7{16'h0708}};
$display("%h", temp);
end
task test_unpack;
input logic [23:0] in;
logic [0:0] i;
logic [1:0] j;
logic [2:0] k;
logic [5:0] l;
logic [11:0] m;
{>>byte{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<byte{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{>>bit{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<bit{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{>>7{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
{<<7{i, j, k, l, m}} = in;
$display("%b %b %b %b %b", i, j, k, l, m);
endtask
initial begin
test_unpack(24'h060708);
test_unpack(24'hC02375);
test_unpack(24'h12E3B8);
end
endmodule
test/core/stream_exhaust.sv 0 → 100644
module Streamer(i, l1, r1, l2, r2);
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
input wire [IN_WIDTH-1:0] i;
output wire [OUT_WIDTH-1:0] l1;
output wire [OUT_WIDTH-1:0] r1;
output reg [OUT_WIDTH-1:0] l2;
output reg [OUT_WIDTH-1:0] r2;
if (IN_WIDTH <= OUT_WIDTH) begin
wire [OUT_WIDTH-1:0] lA = {<<CHUNK_SIZE{i}};
wire [OUT_WIDTH-1:0] rA = {>>CHUNK_SIZE{i}};
wire [OUT_WIDTH-1:0] lB;
wire [OUT_WIDTH-1:0] rB;
assign lB = {<<CHUNK_SIZE{i}};
assign rB = {>>CHUNK_SIZE{i}};
assign l1 = lA == lB ? lA : 'x;
assign r1 = rA == rB ? rA : 'x;
end
if (OUT_WIDTH <= IN_WIDTH) begin
always @* {<<CHUNK_SIZE{l2}} = i;
always @* {>>CHUNK_SIZE{r2}} = i;
end
endmodule
test/core/stream_exhaust.v 0 → 100644
module Streamer(i, l1, r1, l2, r2);
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
input wire [IN_WIDTH-1:0] i;
output wire [OUT_WIDTH-1:0] l1;
output wire [OUT_WIDTH-1:0] r1;
output reg [OUT_WIDTH-1:0] l2;
output reg [OUT_WIDTH-1:0] r2;
function [IN_WIDTH-1:0] stream_left;
input [IN_WIDTH-1:0] inp;
integer idx;
localparam remainder = IN_WIDTH % CHUNK_SIZE;
localparam remainder_fake = remainder ? remainder : 1;
begin
for (idx = 0; idx + CHUNK_SIZE <= IN_WIDTH; idx = idx + CHUNK_SIZE)
stream_left[IN_WIDTH - idx - 1 -: CHUNK_SIZE] = inp[idx+:CHUNK_SIZE];
if (remainder)
stream_left[0+:remainder_fake] = inp[idx+:remainder_fake];
end
endfunction
function [OUT_WIDTH-1:0] pad;
input [IN_WIDTH-1:0] inp;
pad = IN_WIDTH > OUT_WIDTH
? inp >> IN_WIDTH - OUT_WIDTH
: inp << OUT_WIDTH - IN_WIDTH
;
endfunction
generate
if (IN_WIDTH <= OUT_WIDTH) begin
assign l1 = pad(stream_left(i));
assign r1 = pad(i);
end
if (OUT_WIDTH <= IN_WIDTH) begin
always @* l2 = pad(stream_left(i));
always @* r2 = pad(i);
end
endgenerate
endmodule
test/core/stream_exhaust_tb.v 0 → 100644
module Tester;
parameter IN_WIDTH = 0;
parameter OUT_WIDTH = 0;
parameter CHUNK_SIZE = 0;
reg [IN_WIDTH-1:0] i;
wire [OUT_WIDTH-1:0] l1, l2;
wire [OUT_WIDTH-1:0] r1, r2;
Streamer #(IN_WIDTH, OUT_WIDTH, CHUNK_SIZE)
streamer(i, l1, r1, l2, r2);
localparam DELAY = 8 * (CHUNK_SIZE + 8 * (OUT_WIDTH + 8 * IN_WIDTH));
initial #DELAY;
integer idx;
initial begin
for (idx = 0; idx < IN_WIDTH; idx = idx + 1) begin
i = 1 << idx;
#1 $display("INW=%0d OUTW=%0d CS=%0d i=%b l1=%b r1=%b l2=%b r2=%b",
IN_WIDTH, OUT_WIDTH, CHUNK_SIZE, i, l1, r1, l2, r2);
end
end
endmodule
module top;
generate
genvar i, o, c;
for (i = 1; i <= 8; i = i + 1)
for (o = 1; o <= 8; o = o + 1)
for (c = 1; c <= i; c = c + 1)
Tester #(i, o, c) tester();
endgenerate
endmodule
test/core/string.sv 0 → 100644
module top;
localparam FOO = "some useful string";
localparam type T = type(FOO);
localparam T BAR = "some other useful string"; // clipped
initial $display("'%s' '%s'", FOO, BAR);
endmodule
test/core/string.v 0 → 100644
module top;
localparam FOO = "some useful string";
localparam WIDTH = $bits("some useful string");
localparam [WIDTH-1:0] BAR = "some other useful string"; // clipped
initial $display("'%s' '%s'", FOO, BAR);
endmodule
test/core/string_param.sv 0 → 100644
`include "string_param.vh"
module Example(inp, out);
parameter PATTERN = "whatever";
parameter UNUSED = 0;
localparam IN_WIDTH = $bits(PATTERN);
localparam OUT_WIDTH = `COUNT_ONES(PATTERN);
input [IN_WIDTH - 1:0] inp;
output [OUT_WIDTH - 1:0] out;
if (PATTERN[0])
assign out[0] = inp[0];
for (genvar j = 1; j < IN_WIDTH; ++j)
if (PATTERN[j])
assign out[`COUNT_ONES(PATTERN[j - 1:0])] = inp[j];
endmodule
test/core/string_param.v 0 → 100644
`include "string_param.vh"
module Example(inp, out);
parameter PATTERN = "whatever";
parameter IN_WIDTH = $bits(PATTERN);
localparam OUT_WIDTH = `COUNT_ONES(PATTERN);
input wire [IN_WIDTH - 1:0] inp;
output wire [OUT_WIDTH - 1:0] out;
if (PATTERN[0])
assign out[0] = inp[0];
genvar j;
for (j = 1; j < IN_WIDTH; j = j + 1)
if (PATTERN[j])
assign out[`COUNT_ONES(PATTERN[j - 1:0])] = inp[j];
endmodule
test/core/string_param.vh 0 → 100644
`define COUNT_ONES(expr) (0 \
+ ((expr) >> 0 & 1'b1) + ((expr) >> 1 & 1'b1) + ((expr) >> 2 & 1'b1) + ((expr) >> 3 & 1'b1) \
+ ((expr) >> 4 & 1'b1) + ((expr) >> 5 & 1'b1) + ((expr) >> 6 & 1'b1) + ((expr) >> 7 & 1'b1) \
+ ((expr) >> 8 & 1'b1) + ((expr) >> 9 & 1'b1) + ((expr) >> 10 & 1'b1) + ((expr) >> 11 & 1'b1) \
+ ((expr) >> 12 & 1'b1) + ((expr) >> 13 & 1'b1) + ((expr) >> 14 & 1'b1) + ((expr) >> 15 & 1'b1) \
+ ((expr) >> 16 & 1'b1) + ((expr) >> 17 & 1'b1) + ((expr) >> 18 & 1'b1) + ((expr) >> 19 & 1'b1) \
+ ((expr) >> 20 & 1'b1) + ((expr) >> 21 & 1'b1) + ((expr) >> 22 & 1'b1) + ((expr) >> 23 & 1'b1) \
+ ((expr) >> 24 & 1'b1) + ((expr) >> 25 & 1'b1) + ((expr) >> 26 & 1'b1) + ((expr) >> 27 & 1'b1) \
+ ((expr) >> 28 & 1'b1) + ((expr) >> 29 & 1'b1) + ((expr) >> 30 & 1'b1) + ((expr) >> 31 & 1'b1) \
)
module top;
reg [31:0] data;
`define TEST(idx, pattern, in_width, out_width) \
localparam p``idx = pattern; \
wire [in_width - 1:0] i``idx; \
wire [out_width - 1:0] o``idx; \
assign i``idx = data[0+:in_width]; \
Example #(p``idx, in_width) e``idx(i``idx, o``idx);
`TEST(1, 5'b10101, 5, 3)
`TEST(2, 10'b1110001111, 10, 7)
integer i;
initial begin
data = 0;
for (i = 0; i < 100; i = i + 1) begin
data = 1664525 * data + 1013904223;
#1 $display("%b %b %b", data, o1, o2);
end
end
endmodule
test/core/struct_array.sv 0 → 100644
typedef struct packed {
logic x;
logic [3:0] y;
logic [1:0] z;
} Struct_t;
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input Struct_t [WIDTH-1:0] in;
input logic [$clog2(WIDTH)-1:0] select;
output logic a;
output logic [3:0] b;
output logic [1:0] c;
assign a = in[select].x;
assign b = in[select].y;
assign c = in[select].z;
endmodule
test/core/struct_array.v 0 → 100644
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input wire [WIDTH*7-1:0] in;
input wire [$clog2(WIDTH)-1:0] select;
output wire a;
output wire [3:0] b;
output wire [1:0] c;
wire [6:0] p;
assign p = in[select*7+:7];
assign a = p[6:6];
assign b = p[5:2];
assign c = p[1:0];
endmodule
test/core/struct_array_field.sv 0 → 100644
module main;
typedef struct packed {
logic [1:0][2:0] x;
logic [0:2][1:0] y;
logic z;
} foo_t;
foo_t foo;
initial begin
$monitor($time, " %b %b %b %b %b %b %b %b",
foo, foo.x, foo.y, foo.z,
foo.x[0], foo.x[0][0], foo.y[0], foo.y[0][0]);
#1; foo.z = 0;
#1; foo.y = 0;
#1; foo.y[0] = '1;
#1; foo.y[1] = '1;
#1; foo.y[1][1] = 0;
#1; foo.y[0][0] = 1;
#1; foo.y[0][1] = 1;
#1; foo.x = 0;
#1; foo.x[0] = '1;
#1; foo.x[1] = '1;
#1; foo.x[1][1] = 0;
#1; foo.x[0][0] = 1;
#1; foo.x[0][1] = 1;
end
endmodule
module top;
endmodule
test/core/struct_array_field.v 0 → 100644
module main;
reg [2:0] foo_x_1;
reg [2:0] foo_x_0;
reg [1:0] foo_y_2;
reg [1:0] foo_y_1;
reg [1:0] foo_y_0;
wire [5:0] foo_x;
wire [5:0] foo_y;
assign foo_x = {foo_x_1, foo_x_0};
assign foo_y = {foo_y_0, foo_y_1, foo_y_2};
reg foo_z;
wire [12:0] foo;
assign foo = {foo_x, foo_y, foo_z};
initial begin
$monitor($time, " %b %b %b %b %b %b %b %b",
foo, foo_x, foo_y, foo_z,
foo_x_0, foo_x_0[0], foo_y_0, foo_y_0[0]);
#1; foo_z = 0;
#1; {foo_y_0, foo_y_1, foo_y_2} = 0;
#1; foo_y_0 = 1'sb1;
#1; foo_y_1 = 1'sb1;
#1; foo_y_1[1] = 0;
#1; foo_y_0[0] = 1;
#1; foo_y_0[1] = 1;
#1; {foo_x_1, foo_x_0} = 0;
#1; foo_x_0 = 1'sb1;
#1; foo_x_1 = 1'sb1;
#1; foo_x_1[1] = 0;
#1; foo_x_0[0] = 1;
#1; foo_x_0[1] = 1;
end
endmodule
module top;
endmodule
test/core/struct_array_inline.sv 0 → 100644
module top;
typedef struct packed {
bit a, b;
} T;
localparam T FOO [4] = '{
'{ 0, 0 },
'{ 0, 1 },
'{ 1, 0 },
'{ 1, 1 }
};
initial begin
$display(FOO[0].a);
$display(FOO[0].b);
$display(FOO[2].a);
$display(FOO[2].b);
end
endmodule
test/basic/package_pattern.v → test/core/struct_array_inline.v
module top; module top;
reg [1:0] w;
initial begin initial begin
w <= 2'b00; $display(1'b0);
$display("%b", w); $display(1'b0);
$display(1'b1);
$display(1'b0);
end end
endmodule endmodule
test/core/struct_array_param.sv 0 → 100644
typedef struct packed {
logic [2:0] a;
logic [1:0] b;
logic [3:0] c;
} foo_s;
parameter foo_s [1:0] foo = {
'{ a: 2, b: 1, c: 0 },
'{ a: 1, b: 0, c: 2 }
};
module top;
initial begin
$display(foo[0]);
$display(foo[1]);
end
endmodule
test/core/struct_array_param.v 0 → 100644
module top;
parameter foo_1 = { 3'b010, 2'b01, 4'b0000 };
parameter foo_0 = { 3'b001, 2'b00, 4'b0010 };
initial begin
$display(foo_0);
$display(foo_1);
end
endmodule
test/core/struct_array_tb.v 0 → 100644
module top;
reg [56-1:0] in;
reg [2:0] select;
wire a;
wire [3:0] b;
wire [1:0] c;
Unpacker unpacker(in, select, a, b, c);
initial begin
$monitor("%d: %01b %04b %02b", select, a, b, c);
in = 'b01111011011011101111100111110111001010001011100110101000;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
select = 4; #1;
select = 5; #1;
select = 6; #1;
select = 7; #1;
$finish;
end
// 0 1010 00
// 1 1100 11
// 0 1000 10
// 0 1110 01
// 0 0111 11
// 1 0111 11
// 1 0110 11
// 0 1111 01
endmodule
test/core/struct_bit_struct.sv 0 → 100644
typedef struct packed {
logic [3:0] a;
logic [3:0] b;
} pair;
typedef struct packed {
pair [1:0] x;
pair [1:0] y;
} pair_list_pair;
module Example(data, p1, p2, out_x, out_y);
input pair_list_pair data;
input logic p1;
input logic p2;
output logic [3:0] out_x;
output logic [3:0] out_y;
assign out_x = p2 ? data.x[p1].a : data.x[p1].b;
assign out_y = p2 ? data.y[p1].a : data.y[p1].b;
endmodule
test/core/struct_bit_struct.v 0 → 100644
module Example(data, p1, p2, out_x, out_y);
input wire [31:0] data;
input wire p1, p2;
output wire [3:0] out_x;
output wire [3:0] out_y;
assign out_x = p2 ? data[p1 * 8 + 20 +:4] : data[p1 * 8 + 16 +:4];
assign out_y = p2 ? data[p1 * 8 + 4 +:4] : data[p1 * 8 + 0 +:4];
endmodule
test/core/struct_bit_struct_tb.v 0 → 100644
module top;
reg [31:0] data;
reg p1, p2;
wire [3:0] out_x;
wire [3:0] out_y;
Example example(data, p1, p2, out_x, out_y);
task exhaust;
begin
#1 p1 = 0;
#1 p2 = 0;
#1 p1 = 0;
#1 p2 = 1;
#1 p1 = 1;
#1 p2 = 0;
#1 p1 = 1;
#1 p2 = 1;
end
endtask
initial begin
$monitor("%2d %b %b %b %b %b", $time,
data, p1, p2, out_x, out_y);
#1 data = 32'ha7107338;
exhaust;
#1 data = 32'h8f8259e4;
exhaust;
#1 data = 32'h80ad046a;
exhaust;
#1 data = 32'hbf93017e;
exhaust;
#1 data = 32'he6458a2d;
exhaust;
end
endmodule
test/core/struct_default.sv 0 → 100644
module top;
typedef struct packed {
logic a;
logic b;
} foo_t;
foo_t foo;
initial begin
foo = '{a: 1'b1, default: '0};
$display(foo, foo.a, foo.b);
end
endmodule
test/core/struct_default.v 0 → 100644
module top;
reg [1:0] foo = {1'b1, 1'b0};
initial $display(foo, foo[1], foo[0]);
endmodule
test/core/struct_hier_bit.sv 0 → 100644
module top;
if (1) begin : blk
struct packed {
logic x, y;
} [1:0] s;
end
assign blk.s[0].x = 0;
assign top.blk.s[0].y = 1;
assign top.blk.s[1].x = 1;
assign blk.s[1].y = 0;
initial #1 $display("%b", blk.s);
endmodule
test/core/struct_hier_bit.v 0 → 100644
module top;
if (1) begin : blk
wire [3:0] s;
end
assign blk.s = 4'b1001;
initial #1 $display("%b", blk.s);
endmodule
test/core/struct_ident_scope.sv 0 → 100644
`define DUMP(id) \
begin \
x = 1'sb1; \
$display(`"id: access a=%b b=%b`", x.a, x.b); \
x = '{ a: 1'sb1, b: 1'sbz }; \
$display(`"id: literal x=%b`", x); \
end
module top;
parameter A = 2;
parameter B = 3;
struct packed {
logic [A-1:0] a;
logic [B-1:0] b;
} x;
initial `DUMP(0)
if (1) begin : blk
localparam A = 10;
localparam B = 11;
initial `DUMP(1)
end
initial begin
localparam A = 10;
localparam B = 11;
`DUMP(2)
end
endmodule
test/core/struct_ident_scope.v 0 → 100644
`define DUMP(id) \
begin \
x = 1'sb1; \
$display(`"id: access a=%b b=%b`", x[0+:A], x[A+:B]); \
x = { {A {1'sb1}}, {B {1'sbz}} }; \
$display(`"id: literal x=%b`", x); \
end
module top;
parameter A = 2;
parameter B = 3;
reg [A+B-1:0] x;
initial `DUMP(0)
if (1) begin : blk
localparam _A = 10;
localparam _B = 11;
initial `DUMP(1)
end
initial begin : foo
localparam _A = 10;
localparam _B = 11;
`DUMP(2)
end
endmodule
test/core/struct_integer.sv 0 → 100644
module top;
typedef struct packed {
integer a, b, c;
} S;
S s = '{a: 1, b: 2, c: 3};
initial #1 $display("%b %b %b %b", s, s.a, s.b, s.c);
endmodule
test/basic/package_export_nothing.v → test/core/struct_integer.v
module top; module top;
localparam Bar = 2; wire [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
initial $display(Bar); initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
endmodule endmodule
test/core/struct_nested_cast.sv 0 → 100644
package PKG;
typedef struct packed {
logic f;
} foo_t;
endpackage
module top;
typedef struct packed {
PKG::foo_t f;
} local_t;
local_t w;
initial begin
w <= local_t'(1'sb1);
$display("%b", w);
end
endmodule
test/core/struct_nested_cast.v 0 → 100644
module top;
reg w;
initial begin
w <= 1'b1;
$display("%b", w);
end
endmodule
test/core/struct_param.sv 0 → 100644
module Module #(parameter type T, parameter N);
T t;
type(t.a) x;
type(t.b) y;
initial begin
$display("$bits(T)=", $bits(T));
$display("$bits(t)=", $bits(t));
$display("$bits(t.a)=", $bits(t.a));
$display("$bits(t.b)=", $bits(t.b));
$display("$bits(x)=", $bits(x));
$display("$bits(y)=", $bits(y));
$display("$bits(N)=", $bits(N));
$display("N=", N);
end
endmodule
module top;
typedef struct packed {
logic a;
logic [2] b;
} Struct1;
typedef struct packed {
logic [5] a;
Struct1 b;
logic [2] c;
logic d;
} Struct2;
Module #(Struct1, $bits(Struct1)) m1();
Module #(Struct2, $bits(Struct2)) m2();
endmodule
test/core/struct_param.v 0 → 100644
module Module1 #(parameter N = 1);
initial begin
$display("$bits(T)=", 3);
$display("$bits(t)=", 3);
$display("$bits(t.a)=", 1);
$display("$bits(t.b)=", 2);
$display("$bits(x)=", 1);
$display("$bits(y)=", 2);
$display("$bits(N)=", 32);
$display("N=", N);
end
endmodule
module Module2 #(parameter N = 1);
initial begin
$display("$bits(T)=", 11);
$display("$bits(t)=", 11);
$display("$bits(t.a)=", 5);
$display("$bits(t.b)=", 3);
$display("$bits(x)=", 5);
$display("$bits(y)=", 3);
$display("$bits(N)=", 32);
$display("N=", N);
end
endmodule
module top;
Module1 #(3) m1();
Module2 #(11) m2();
endmodule
test/core/struct_part_select.sv 0 → 100644
module Example;
typedef struct packed {
logic [10:4] a;
logic [1:3] bx;
logic [3:1] by;
logic [3:4][5:7] cw;
logic [4:3][5:7] cx;
logic [3:4][7:5] cy;
logic [4:3][7:5] cz;
} T;
T t;
initial begin
$monitor("%2d %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b", $time,
t, t.a, t.bx, t.by,
t.cw, t.cw[3], t.cw[4],
t.cx, t.cx[3], t.cx[4],
t.cy, t.cy[3], t.cy[4],
t.cz, t.cz[3], t.cz[4]
);
#1 t.a = 1;
#1 t.a[5+:2] = '1;
#1 t.a[8-:3] = '1;
#1 t.a[10] = 1;
#1 t.a[7] = 0;
#1 t.bx[1+:1] = 1;
#1 t.bx[1:2] = 1;
#1 t.bx[3] = 0;
#1 t.bx[3-:2] = 1;
#1 t.bx[2] = 0;
#1 t.by[1+:1] = 1;
#1 t.by[2:1] = 1;
#1 t.by[3] = 0;
#1 t.by[3-:2] = 1;
#1 t.by[2] = 0;
#1 t.cw[3][6+:1] = 1;
#1 t.cw[3][7-:2] = 1;
#1 t.cw[3][5+:2] = 0;
#1 t.cw[3][6:7] = 2'b10;
#1 t.cw[3][6:7] = 2'b01;
#1 t.cw[3:4] = '1;
#1 t.cw[4][5] = 0;
#1 t.cw[4][6:7] = 0;
#1 t.cw[3+:2] = 6'b010011;
#1 t.cw[4-:2] = 6'b101011;
#1 t.cx[3][6+:1] = 1;
#1 t.cx[3][7-:2] = 1;
#1 t.cx[3][5+:2] = 0;
#1 t.cx[3][6:7] = 2'b10;
#1 t.cx[3][6:7] = 2'b01;
#1 t.cx[4:3] = '1;
#1 t.cx[4][5] = 0;
#1 t.cx[4][6:7] = 0;
#1 t.cx[3+:2] = 6'b010011;
#1 t.cx[4-:2] = 6'b101011;
#1 t.cy[3][6+:1] = 1;
#1 t.cy[3][7-:2] = 1;
#1 t.cy[3][5+:2] = 0;
#1 t.cy[3][7:6] = 2'b10;
#1 t.cy[3][7:6] = 2'b01;
#1 t.cy[3:4] = '1;
#1 t.cy[4][5] = 0;
#1 t.cy[4][7:6] = 0;
#1 t.cy[3+:2] = 6'b010011;
#1 t.cy[4-:2] = 6'b101011;
#1 t.cz[3][6+:1] = 1;
#1 t.cz[3][7-:2] = 1;
#1 t.cz[3][5+:2] = 0;
#1 t.cz[3][7:6] = 2'b10;
#1 t.cz[3][7:6] = 2'b01;
#1 t.cz[4:3] = '1;
#1 t.cz[4][5] = 0;
#1 t.cz[4][7:6] = 0;
#1 t.cz[3+:2] = 6'b010011;
#1 t.cz[4-:2] = 6'b101011;
end
endmodule
module top;
endmodule
test/core/struct_part_select_param.v 0 → 100644
// The reference output for this test should match that of the
// struct_part_select test.
`include "struct_part_select.v"
test/core/struct_scope.sv 0 → 100644
module top;
typedef struct packed {
logic x;
logic [1:0] y;
} A;
typedef struct packed {
logic [2:0] x;
logic [3:0] y;
} B;
typedef struct packed {
logic [4:0] x;
logic [5:0] y;
B z;
} C;
A a;
B b;
C c;
generate
begin : foo
typedef struct packed {
logic [6:0] x;
logic [7:0] y;
} B;
typedef struct packed {
logic [8:0] x;
logic [9:0] y;
B z;
} D;
A a;
B b;
C c;
D d;
end
endgenerate
`define INSPECT_SIZE(expr) $display(`"expr -> %0d`", $bits(expr));
`define INSPECT_DATA(expr) $display(`"expr -> %b`", expr);
initial begin
`INSPECT_SIZE(a);
`INSPECT_SIZE(a.x);
`INSPECT_SIZE(a.y);
`INSPECT_SIZE(b);
`INSPECT_SIZE(b.x);
`INSPECT_SIZE(b.y);
`INSPECT_SIZE(c);
`INSPECT_SIZE(c.x);
`INSPECT_SIZE(c.y);
`INSPECT_SIZE(c.z);
`INSPECT_SIZE(c.z.x);
`INSPECT_SIZE(c.z.y);
`INSPECT_SIZE(foo.a);
`INSPECT_SIZE(foo.a.x);
`INSPECT_SIZE(foo.a.y);
`INSPECT_SIZE(foo.b);
`INSPECT_SIZE(foo.b.x);
`INSPECT_SIZE(foo.b.y);
`INSPECT_SIZE(foo.c);
`INSPECT_SIZE(foo.c.x);
`INSPECT_SIZE(foo.c.y);
`INSPECT_SIZE(foo.c.z);
`INSPECT_SIZE(foo.c.z.x);
`INSPECT_SIZE(foo.c.z.y);
`INSPECT_SIZE(foo.d);
`INSPECT_SIZE(foo.d.x);
`INSPECT_SIZE(foo.d.y);
`INSPECT_SIZE(foo.d.z);
`INSPECT_SIZE(foo.d.z.x);
`INSPECT_SIZE(foo.d.z.y);
`INSPECT_DATA(a);
`INSPECT_DATA(b);
`INSPECT_DATA(c);
`INSPECT_DATA(foo.a);
`INSPECT_DATA(foo.b);
`INSPECT_DATA(foo.c);
`INSPECT_DATA(foo.d);
end
endmodule
test/core/struct_scope.v 0 → 100644
module top;
wire [2:0] a;
wire [6:0] b;
wire [17:0] c;
generate
if (1) begin : foo
wire [2:0] a;
wire [14:0] b;
wire [17:0] c;
wire [33:0] d;
end
endgenerate
`define INSPECT_SIZE(expr, size) $display(`"expr -> %0d`", size);
`define INSPECT_DATA(expr) $display(`"expr -> %b`", expr);
initial begin
`INSPECT_SIZE(a, 3);
`INSPECT_SIZE(a.x, 1);
`INSPECT_SIZE(a.y, 2);
`INSPECT_SIZE(b, 7);
`INSPECT_SIZE(b.x, 3);
`INSPECT_SIZE(b.y, 4);
`INSPECT_SIZE(c, 18);
`INSPECT_SIZE(c.x, 5);
`INSPECT_SIZE(c.y, 6);
`INSPECT_SIZE(c.z, 7);
`INSPECT_SIZE(c.z.x, 3);
`INSPECT_SIZE(c.z.y, 4);
`INSPECT_SIZE(foo.a, 3);
`INSPECT_SIZE(foo.a.x, 1);
`INSPECT_SIZE(foo.a.y, 2);
`INSPECT_SIZE(foo.b, 15);
`INSPECT_SIZE(foo.b.x, 7);
`INSPECT_SIZE(foo.b.y, 8);
`INSPECT_SIZE(foo.c, 18);
`INSPECT_SIZE(foo.c.x, 5);
`INSPECT_SIZE(foo.c.y, 6);
`INSPECT_SIZE(foo.c.z, 7);
`INSPECT_SIZE(foo.c.z.x, 3);
`INSPECT_SIZE(foo.c.z.y, 4);
`INSPECT_SIZE(foo.d, 34);
`INSPECT_SIZE(foo.d.x, 9);
`INSPECT_SIZE(foo.d.y, 10);
`INSPECT_SIZE(foo.d.z, 15);
`INSPECT_SIZE(foo.d.z.x, 7);
`INSPECT_SIZE(foo.d.z.y, 8);
`INSPECT_DATA(a);
`INSPECT_DATA(b);
`INSPECT_DATA(c);
`INSPECT_DATA(foo.a);
`INSPECT_DATA(foo.b);
`INSPECT_DATA(foo.c);
`INSPECT_DATA(foo.d);
end
endmodule
test/core/struct_shadow.v 0 → 100644
// While this might look silly, you'll notice that the sections are actually
// different. We are ensuring that the correct struct definitions are being used
// in each scope.
module top;
reg [2:0] a = 3'b111;
reg [2:0] b = 3'b111;
reg [2:0] c = 3'b111;
reg [2:0] d = 3'b111;
reg [2:0] e = 3'b111;
reg [2:0] f = 3'b111;
integer i = 2;
integer j = 2;
integer k = 2;
initial begin
$display("A: 000 -> 000000");
$display("A: 001 -> 121424");
$display("A: 010 -> 214142");
$display("A: 011 -> 335566");
$display("A: 100 -> 442211");
$display("A: 101 -> 563635");
$display("A: 110 -> 656353");
$display("A: 111 -> 777777");
$display("B: 000 -> 000000");
$display("B: 001 -> 214241");
$display("B: 010 -> 141422");
$display("B: 011 -> 355663");
$display("B: 100 -> 422114");
$display("B: 101 -> 636355");
$display("B: 110 -> 563536");
$display("B: 111 -> 777777");
$display("C: 000 -> 000000");
$display("C: 001 -> 142412");
$display("C: 010 -> 414221");
$display("C: 011 -> 556633");
$display("C: 100 -> 221144");
$display("C: 101 -> 363556");
$display("C: 110 -> 635365");
$display("C: 111 -> 777777");
$display("D: 000 -> 000000");
$display("D: 001 -> 424121");
$display("D: 010 -> 142214");
$display("D: 011 -> 566335");
$display("D: 100 -> 211442");
$display("D: 101 -> 635563");
$display("D: 110 -> 353656");
$display("D: 111 -> 777777");
$display("E: 000 -> 000000");
$display("E: 001 -> 241214");
$display("E: 010 -> 422141");
$display("E: 011 -> 663355");
$display("E: 100 -> 114422");
$display("E: 101 -> 355636");
$display("E: 110 -> 536563");
$display("E: 111 -> 777777");
$display("F: 000 -> 000000");
$display("F: 001 -> 412142");
$display("F: 010 -> 221414");
$display("F: 011 -> 633556");
$display("F: 100 -> 144221");
$display("F: 101 -> 556363");
$display("F: 110 -> 365635");
$display("F: 111 -> 777777");
end
endmodule
test/core/struct_tern.sv 0 → 100644
module Example(flag, out);
typedef struct packed {
logic a, b;
} T;
output T out;
input logic flag;
assign out =
flag
? '{ a: 1'b1, b: 1'b0 }
: '{ a: 1'b1, b: 1'b1 }
;
endmodule
test/core/struct_tern.v 0 → 100644
module Example(flag, out);
output wire [1:0] out;
input wire flag;
assign out = flag ? 2'b10 : 2'b11;
endmodule
test/core/struct_tern_tb.v 0 → 100644
module top;
reg flag;
wire [1:0] out;
Example example(flag, out);
initial begin
$monitor("%2d %b %b", $time, flag, out);
#1 flag = 0;
#1 flag = 1;
#1 flag = 0;
#1 flag = 1;
end
endmodule
test/core/struct_unit_array.sv 0 → 100644
module top;
typedef struct packed {
logic a, b;
} T;
typedef struct packed {
logic x;
T y;
} S;
localparam WIDTH = 1;
S [WIDTH] s = '{
'{x: 1, y: '{a: 1, b: 0}}
};
initial #1 $display("%b", s);
endmodule
test/core/struct_unit_array.v 0 → 100644
module top;
wire [2:0] s = 3'b110;
initial #1 $display("%b", s);
endmodule
test/core/subroutine.sv 0 → 100644
class C #(
parameter X = 1
);
static task dump;
$display("C#(%0d)::dump()", X);
endtask
endclass
package P;
task dump;
$display("P::dump()");
endtask
endpackage
module top;
task dump;
$display("dump()");
endtask
`define TEST(subroutine) \
initial begin subroutine; end \
initial begin subroutine(); end \
initial begin ; subroutine; end \
initial begin ; subroutine(); end
`TEST(dump)
`TEST(P::dump)
`TEST(C#(1)::dump)
endmodule
test/core/subroutine.v 0 → 100644
module top;
`define TEST(subroutine) \
initial repeat (4) $display(`"subroutine()`");
`TEST(dump)
`TEST(P::dump)
`TEST(C#(1)::dump)
endmodule
test/core/tf_block.sv 0 → 100644
module top;
function [2:0] f;
input [2:0] n;
n += 1;
return n + 3;
endfunction
task t;
$display("hello");
$display("world");
endtask
initial t();
initial $display("f(0) = ", f(0));
initial $display("f(1) = ", f(1));
endmodule
test/core/tf_block.v 0 → 100644
module top;
function [2:0] f;
input [2:0] n;
f = n + 4;
endfunction
task t;
begin
$display("hello");
$display("world");
end
endtask
initial t();
initial $display("f(0) = ", f(0));
initial $display("f(1) = ", f(1));
endmodule
test/core/time.sv 0 → 100644
`timescale 1ns / 10ps
timeunit 100ps;
timeprecision 1ps;
module top_1;
`timescale 1ns / 10ps
timeunit 1ps;
timeprecision 1ps;
endmodule
module top_2;
timeunit 100ps / 10fs;
endmodule
module top_3;
timeunit 10.0ps / 10fs;
endmodule
module top_4;
timeunit 100ps;
timeprecision 10fs;
endmodule
module top;
initial $display("Hello!");
endmodule
test/core/time.v 0 → 100644
module top;
initial $display("Hello!");
endmodule
test/core/top_tf.sv 0 → 100644
task foo;
$display("task foo() called");
endtask
function bar;
input [2:0] n;
bar = baz(n + 1);
endfunction
function baz;
input [2:0] n;
baz = n * 2;
endfunction
localparam PARAM = 37;
module top;
initial foo();
initial $display("bar(0) = %d", bar(0));
initial $display("PARAM = %d", PARAM);
endmodule
test/core/top_tf.v 0 → 100644
module top;
task foo;
$display("task foo() called");
endtask
function bar;
input [2:0] n;
bar = baz(n + 1);
endfunction
function baz;
input [2:0] n;
baz = n * 2;
endfunction
localparam PARAM = 37;
initial foo();
initial $display("bar(0) = %d", bar(0));
initial $display("PARAM = %d", PARAM);
endmodule
test/core/trailing_commas.sv 0 → 100644
module ModuleA #(P=1,) (inp,);
input inp;
initial $display("ModuleA P=%0d inp=%b", P, inp);
endmodule
module ModuleB #(parameter P,) (input inp,);
initial $display("ModuleB P=%0d inp=%b", P, inp);
endmodule
module top;
ModuleA #(1,) a(1'b1,);
ModuleB #(.P(1),) b(.inp(1'b1),);
endmodule
test/core/trailing_commas.v 0 → 100644
module ModuleA #(parameter P = 1) (input inp);
initial $display("ModuleA P=%0d inp=%b", P, inp);
endmodule
module ModuleB #(parameter P = 0) (input inp);
initial $display("ModuleB P=%0d inp=%b", P, inp);
endmodule
module top;
ModuleA #(1) a(1'b1);
ModuleB #(.P(1)) b(.inp(1'b1));
endmodule
test/core/typedef_ident_scope.sv 0 → 100644
`define DUMP(id) \
$display(`"id: $bits(T) = %0d, $left(T) = %0d, $right(T) = %0d`", \
$bits(T), $left(T), $right(T))
module top;
parameter A = 1;
parameter B = 2;
parameter ONE = 1;
typedef logic [A:B] T;
initial `DUMP(X1);
if (1) begin : blk
localparam A = ONE * 3;
localparam B = ONE * 4;
initial `DUMP(X2);
if (1) begin : nest
typedef logic [A:B] T;
initial `DUMP(Y0);
end
end
initial begin
localparam A = ONE * 5;
localparam B = ONE * 6;
`DUMP(X3);
begin
localparam type T = logic [A:B];
`DUMP(Z0);
end
end
endmodule
test/core/typedef_ident_scope.v 0 → 100644
`define DUMP(id, A, B) \
$display(`"id: $bits(T) = %0d, $left(T) = %0d, $right(T) = %0d`", \
A >= B ? A - B + 1: B - A + 1, A, B)
module top;
parameter A = 1;
parameter B = 2;
parameter ONE = 1;
initial `DUMP(X1, A, B);
if (1) begin : blk
localparam _A = ONE * 3;
localparam _B = ONE * 4;
initial `DUMP(X2, A, B);
if (1) begin : nest
initial `DUMP(Y0, _A, _B);
end
end
initial begin : foo
localparam _A = ONE * 5;
localparam _B = ONE * 6;
`DUMP(X3, A, B);
`DUMP(Z0, _A, _B);
end
endmodule
test/core/typedef_scope.sv 0 → 100644
module Example;
parameter FLAG_1 = 0;
parameter FLAG_2 = 0;
typedef logic [2:0] T;
if (FLAG_1) begin
typedef logic [1:0] T;
T t = 0;
initial $display("2 %b", t);
if (FLAG_2) begin
typedef logic [3:0] T;
T t = 0;
initial $display("4 %b", t);
end
end
else begin
typedef logic T;
T t = 0;
initial $display("1 %b", t);
end
T t = 0;
initial $display("3 %b", t);
endmodule
module top;
Example #(0, 0) a();
Example #(1, 0) b();
Example #(0, 1) c();
Example #(1, 1) d();
endmodule
test/core/typedef_scope.v 0 → 100644
module Example;
parameter FLAG_1 = 0;
parameter FLAG_2 = 0;
if (FLAG_1) begin
wire [1:0] t = 0;
initial $display("2 %b", t);
if (FLAG_2) begin
wire [3:0] t = 0;
initial $display("4 %b", t);
end
end
else begin
wire t = 0;
initial $display("1 %b", t);
end
wire [2:0] t = 0;
initial $display("3 %b", t);
endmodule
module top;
Example #(0, 0) a();
Example #(1, 0) b();
Example #(0, 1) c();
Example #(1, 1) d();
endmodule
test/core/typename_cast.sv 0 → 100644
module Example;
parameter type T = logic [3:0];
T v = T'('1);
initial #1 $display("%b", v);
endmodule
module top; Example example(); endmodule
test/core/typename_cast.v 0 → 100644
module Example;
wire [3:0] v = 4'b1111;
initial #1 $display("%b", v);
endmodule
module top; Example example(); endmodule
test/core/typeof.sv 0 → 100644
module top;
function f;
input x;
f = 1'b1 ^ x;
$display("f(%b) called", x);
endfunction
task t;
input x;
$display("t(%b) called", x);
endtask
initial begin
type(f(0)) x = f(0);
type(x) y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", $bits(x));
$display("%b", $bits(type(x)));
$display("%b", $bits(logic [0:1+$bits(type(x))]));
f(1);
void'(f(0));
t(1);
end
parameter FLAG = 1;
initial begin
logic [4:1] x = 4'b1011;
type(x ^ 3'b111) y = x ^ 3'b111;
type(x ^ 5'b11111) z = x ^ 5'b11111;
type({8 {x}}) a = {8 {x}};
type({x, y}) b = {x, y};
type(FLAG ? x : y) c = FLAG ? x : y;
type(!FLAG ? x : y) d = !FLAG ? x : y;
type($clog2(x)) e = $clog2(x);
type(!e) f = !e;
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
$display("%b %d %d", a, $left(a), $right(a));
$display("%b %d %d", b, $left(b), $right(b));
$display("%b %d %d", c, $left(c), $right(c));
$display("%b %d %d", d, $left(d), $right(d));
$display("%b %d %d", e, $left(e), $right(e));
$display("%b %d", f, $bits(f));
end
parameter W = 4;
initial begin
type('1) w = '1;
logic [W-1:0] x = 4'hA;
type(FLAG ? x : '1) y = FLAG ? x : '1;
type(!FLAG ? y : '1) z = !FLAG ? y : '1;
$display("%b %d %d", w, $left(w), $right(w));
$display("%b %d %d", x, $left(x), $right(x));
$display("%b %d %d", y, $left(y), $right(y));
$display("%b %d %d", z, $left(z), $right(z));
end
initial begin
type(1) w = 1;
type(-1) x = -1;
type(32'hffff_ffff) y = 32'hffff_ffff;
type(32'shffff_ffff) z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, $left(w), $right(w));
$display("%b %d %d %d", x, x, $left(x), $right(x));
$display("%b %d %d %d", y, y, $left(y), $right(y));
$display("%b %d %d %d", z, z, $left(z), $right(z));
end
for (genvar i = 0; i < 2; ++i)
initial begin
type(i) a;
a = ~i;
$display("%b %d %d %d", i, i, $left(i), $right(i));
$display("%b %d %d %d", a, a, $left(a), $right(a));
end
localparam X = 5'b10110;
localparam Y = X + 6'b00001;
localparam [7:0] Z = 234;
initial begin
type(X) tX = X;
type(Y) tY = Y;
type(Z) tZ = Z;
$display("%b %d %d %d", X, X, $left(X), $right(X));
$display("%b %d %d %d", Y, Y, $left(Y), $right(Y));
$display("%b %d %d %d", Z, Z, $left(Z), $right(Z));
$display("%b %d %d %d", tX, tX, $left(tX), $right(tX));
$display("%b %d %d %d", tY, tY, $left(tY), $right(tY));
$display("%b %d %d %d", tZ, tZ, $left(tZ), $right(tZ));
end
endmodule
test/core/typeof.v 0 → 100644
module top;
function f;
input x;
begin
f = 1'b1 ^ x;
$display("f(%b) called", x);
end
endfunction
task t;
input x;
$display("t(%b) called", x);
endtask
initial begin : block
reg x, y;
x = f(0);
y = ~x;
$display("%b", x);
$display("%b", y);
$display("%b", 32'd1);
$display("%b", 32'd1);
$display("%b", 32'd3);
x = f(1);
x = f(0);
t(1);
end
parameter FLAG = 1;
initial begin : block2
reg [4:1] x;
reg [3:0] y;
reg [4:0] z;
reg [31:0] a;
reg [7:0] b;
reg [3:0] c, d;
integer e;
reg f;
x = 4'b1011;
y = x ^ 3'b111;
z = x ^ 5'b11111;
a = {8 {x}};
b = {x, y};
c = FLAG ? x : y;
d = !FLAG ? x : y;
e = $clog2(x);
f = !e;
$display("%b %d %d", x, 4, 1);
$display("%b %d %d", y, 3, 0);
$display("%b %d %d", z, 4, 0);
$display("%b %d %d", a, 31, 0);
$display("%b %d %d", b, 7, 0);
$display("%b %d %d", c, 3, 0);
$display("%b %d %d", d, 3, 0);
$display("%b %d %d", e, 31, 0);
$display("%b %d", f, 1);
end
parameter W = 4;
initial begin : block3
reg w;
reg [W-1:0] x, y, z;
w = 1;
x = 4'hA;
y = FLAG ? x : 4'hF;
z = !FLAG ? y : 4'hF;
$display("%b %d %d", w, 0, 0);
$display("%b %d %d", x, W-1, 0);
$display("%b %d %d", y, W-1, 0);
$display("%b %d %d", z, W-1, 0);
end
initial begin : block4
integer w, x, z;
reg [31:0] y;
w = 1;
x = -1;
y = 32'hffff_ffff;
z = 32'shffff_ffff;
$display("%b %d %d %d", w, w, 31, 0);
$display("%b %d %d %d", x, x, 31, 0);
$display("%b %d %d %d", y, y, 31, 0);
$display("%b %d %d %d", z, z, 31, 0);
end
generate
genvar i;
for (i = 0; i < 2; i = i + 1)
initial begin : block5
localparam a = ~i;
$display("%b %d %d %d", i, i, 31, 0);
$display("%b %d %d %d", a, a, 31, 0);
end
endgenerate
localparam X = 5'b10110;
localparam Y = X + 6'b00001;
localparam [7:0] Z = 234;
initial begin : block5
reg [4:0] tX;
reg [5:0] tY;
reg [7:0] tZ;
tX = X;
tY = Y;
tZ = Z;
$display("%b %d %d %d", X, X, 4, 0);
$display("%b %d %d %d", Y, Y, 5, 0);
$display("%b %d %d %d", Z, Z, 7, 0);
$display("%b %d %d %d", tX, tX, 4, 0);
$display("%b %d %d %d", tY, tY, 5, 0);
$display("%b %d %d %d", tZ, tZ, 7, 0);
end
endmodule
test/core/typeof_alias.sv 0 → 100644
package P;
typedef logic [1:0][2:0] T;
endpackage
module top;
P::T w;
type(w[0]) x;
type(x[0]) y;
type(w[0][0]) z;
type(w[1:0]) a;
type(w[0][1:0]) b;
initial begin
$display("%b %b %b %b", w, x, y, z);
$display("%b %b", a, b);
end
endmodule
test/core/typeof_alias.v 0 → 100644
module top;
wire [5:0] w;
wire [2:0] x;
wire y;
wire z;
wire [5:0] a;
wire [1:0] b;
initial begin
$display("%b %b %b %b", w, x, y, z);
$display("%b %b", a, b);
end
endmodule
test/core/typeof_port.sv 0 → 100644
module Example(inp, out);
input inp;
output out;
type(inp) data;
assign data = ~inp;
assign out = data;
endmodule
test/core/typeof_port.v 0 → 100644
module Example(inp, out);
input inp;
output out;
wire data;
assign data = ~inp;
assign out = data;
endmodule
test/core/typeof_port_tb.v 0 → 100644
module top;
reg inp;
wire out;
Example e(inp, out);
initial begin
$monitor("%0d %b %b", $time, inp, out);
end
endmodule
test/core/typeof_scope.sv 0 → 100644
`define TYPEOF(x) wire [$bits(x) - 1:0]
// The `REF` sections of this test are workarounds for steveicarus/iverilog#483
module top;
genvar i;
if (1) begin : blk
for (i = 0; i < 3; i = i + 1) begin : prev
localparam V = i * 2;
localparam W = V;
wire [W:0] x;
end
for (i = 0; i < 2; i = i + 1) begin : loop
`TYPEOF(prev[i+1].x) x;
if (1) begin : a
localparam j = i - 3;
if (1) begin : b
localparam i = j + 2;
`TYPEOF(prev[i+2].x) x;
if (1) begin : c
localparam j = i - 4;
if (1) begin : d
localparam i = j + 7;
localparam z = i - 1;
`TYPEOF(prev[z].x) x;
if (1) begin : e
localparam i = 0;
`ifdef REF
localparam j = 3;
`else
localparam j = $bits(blk.loop[i].a.b.c.d.x);
`endif
wire [j-1:0] y;
end
end
end
end
end
end
end
`ifdef REF
wire [1*2:0] a;
wire [2*2:0] b;
wire [1*2:0] c;
wire [2*2:0] d;
wire [1*2:0] e;
wire [2*2:0] f;
wire [1*2:0] g;
wire [1*2:0] h;
`else
`TYPEOF(blk.loop[0].x) a;
`TYPEOF(blk.loop[1].x) b;
`TYPEOF(blk.loop[0].a.b.x) c;
`TYPEOF(blk.loop[1].a.b.x) d;
`TYPEOF(blk.loop[0].a.b.c.d.x) e;
`TYPEOF(blk.loop[1].a.b.c.d.x) f;
`TYPEOF(blk.loop[0].a.b.c.d.e.y) g;
`TYPEOF(blk.loop[1].a.b.c.d.e.y) h;
`endif
`define DUMP(x) assign x = 1; initial $display(`"x: %b (%0d bits)`", x, $bits(x));
`DUMP(a) `DUMP(b) `DUMP(c) `DUMP(d) `DUMP(e) `DUMP(f) `DUMP(g) `DUMP(h)
`DUMP(blk.loop[0].x)
`DUMP(blk.loop[1].x)
`DUMP(blk.loop[0].a.b.x)
`DUMP(blk.loop[1].a.b.x)
`DUMP(blk.loop[0].a.b.c.d.x)
`DUMP(blk.loop[1].a.b.c.d.x)
`DUMP(blk.loop[0].a.b.c.d.e.y)
`DUMP(blk.loop[1].a.b.c.d.e.y)
endmodule
test/core/typeof_scope.v 0 → 100644
`define REF 1
`include "typeof_scope.sv"
test/core/typeof_signed.v 0 → 100644
`define MAKE_PRIM(typ, size) \
reg [size-1:0] typ``_unspecified = 1; \
reg [size-1:0] typ``_unsigned = 1; \
reg signed [size-1:0] typ``_signed = 1;
module top;
wire signed x;
wire signed [1:0] y;
assign x = 0;
assign y = 2;
wire signed [1:0] z;
assign z = x % y;
wire [3:0] w;
assign w = z;
initial #1 $display("%b %b %b %b", x, y, z, w);
`MAKE_PRIM(byte, 8)
`MAKE_PRIM(shortint, 16)
`MAKE_PRIM(int, 32)
integer integer_unspecified = 1;
reg [31:0] integer_unsigned = 1;
integer integer_signed = 1;
`MAKE_PRIM(longint, 64)
`MAKE_PRIM(bit, 1)
`MAKE_PRIM(reg, 1)
`MAKE_PRIM(logic, 1)
reg signed [5:0] arr;
endmodule
test/core/unbased_unsized_default.sv 0 → 100644
module Example(inp);
input [4][5] inp;
initial #1 $display("%b", inp);
endmodule
module top;
Example e1('{default:'0});
Example e2('{default:'1});
Example e3('{default:'x});
Example e4('{default:'z});
endmodule
test/core/unbased_unsized_default.v 0 → 100644
module Example(inp);
input [19:0] inp;
initial #1 $display("%b", inp);
endmodule
module top;
Example e1({20 {1'sb0}});
Example e2({20 {1'sb1}});
Example e3({20 {1'sbx}});
Example e4({20 {1'sbz}});
endmodule
test/core/unbound_port.sv 0 → 100644
`ifndef TRAIL
`define TRAIL ,
`endif
module mod #(
parameter [23:0] KEY = "INV"
) (a, b, c);
input wire [31:0] a, b, c;
initial #1 $display("%s a=%0d b=%0d c=%0d", KEY, a, b, c);
endmodule
module top;
mod #("MA0") MA0(, , );
mod #("MA1") MA1(1, , );
mod #("MA2") MA2(1, 2, );
mod #("MA3") MA3(1, 2, 3);
mod #("MA4") MA4(1, , 3);
mod #("MA5") MA5(1, , 3);
mod #("MA6") MA6(, 2, 3);
mod #("MA7") MA7(, , 3);
mod #("MB0") MB0(, , `TRAIL);
mod #("MB1") MB1(1, , `TRAIL);
mod #("MB2") MB2(1, 2, `TRAIL);
mod #("MB3") MB3(1, 2, 3 `TRAIL);
mod #("MB4") MB4(1, , 3 `TRAIL);
mod #("MB5") MB5(1, , 3 `TRAIL);
mod #("MB6") MB6(, 2, 3 `TRAIL);
mod #("MB7") MB7(, , 3 `TRAIL);
endmodule
test/core/unbound_port.v 0 → 100644
`define TRAIL
`include "unbound_port.sv"
test/core/union.sv 0 → 100644
typedef union packed {
logic [4:0] x;
logic [4:0] y;
} A;
typedef union packed {
logic [4:0] x;
logic [0:4] y;
} B;
typedef union packed {
logic [4:0] x;
logic [1:5] y;
} C;
typedef union packed {
logic [4:0] x;
struct packed {
logic [2:0] a;
logic [1:0] b;
} y;
struct packed {
logic [1:0] a;
logic [0:2] b;
} z;
} D;
module wrap;
A a;
B b;
C c;
D d;
localparam delay = 10;
initial begin
$monitor($time, " %b %b", a.x, a.y);
a.x = 5'b01101; #delay;
a.y = 5'b11101; #delay;
$monitor($time, " %b %b", b.x, b.y);
b.x = 5'b01101; #delay;
b.y = 5'b11101; #delay;
$monitor($time, " %b %b", c.x, c.y);
c.x = 5'b01101; #delay;
c.y = 5'b11101; #delay;
$monitor($time, " %b %b {%b %b} %b {%b %b}", d.x, d.y, d.y.a, d.y.b,
d.z, d.z.a, d.z.b);
d.x = 5'b01101; #delay;
d.y = '{ a: 3'b110, b: 2'b01 }; #delay;
d.z = '{ b: 3'b110, a: 2'b01 }; #delay;
d.y.a = 3'b010; #delay;
d.y.b = 2'b10; #delay;
d.z.a = 2'b11; #delay;
d.z.b = 3'b101; #delay;
end
endmodule
test/core/union.v 0 → 100644
module wrap;
initial begin
// This was generated by running the original through VCS.
$display(" 0 01101 01101");
$display(" 10 11101 11101");
$display(" 20 01101 01101");
$display(" 30 11101 11101");
$display(" 40 01101 01101");
$display(" 50 11101 11101");
$display(" 60 01101 01101 {011 01} 01101 {01 101}");
$display(" 70 11001 11001 {110 01} 11001 {11 001}");
$display(" 80 01110 01110 {011 10} 01110 {01 110}");
$display(" 90 01010 01010 {010 10} 01010 {01 010}");
$display(" 110 11010 11010 {110 10} 11010 {11 010}");
$display(" 120 11101 11101 {111 01} 11101 {11 101}");
#130;
end
endmodule
test/core/union_tb.v 0 → 100644
module top;
wrap wrap();
endmodule
test/core/uniop_prec.sv 0 → 100644
module Example(a, b);
input logic [1:0] a;
output logic b;
assign b = !(&a);
endmodule
test/core/uniop_prec.v 0 → 100644
module Example(a, b);
input wire [1:0] a;
output wire b;
assign b = !(&a);
endmodule
test/core/uniop_prec_tb.v 0 → 100644
module top;
reg [1:0] a;
wire b;
Example example(a, b);
initial begin
$monitor("%2d %b %b", $time, a, b);
#1;
#1; a[0] = 1;
#1; a[1] = 1;
#1; a[0] = 1'sbx;
end
endmodule
test/core/unnamed_block_shadow.sv 0 → 100644
`define TEST \
reg x; \
begin \
reg [1:0] x; \
$display("%0d %b", $bits(x), x); \
end \
$display("%0d %b", $bits(x), x);
module top;
task t;
input integer unused;
`TEST
endtask
function f;
input integer unused;
`TEST
endfunction
initial t(f(0));
initial begin
`TEST
end
endmodule
test/core/unnamed_block_shadow.v 0 → 100644
module top;
initial begin : blk
integer i;
reg [1:0] y;
reg x;
for (i = 0; i < 3; i = i + 1) begin
$display("%0d %b", 2, y);
$display("%0d %b", 1, x);
end
end
endmodule
test/core/unpacked_array_depth.sv 0 → 100644
module example(
input wire [7:0] inp,
output wire [7:0] out
);
assign out = ~inp;
endmodule
module top;
reg arr1 [7:0][1:0];
reg arr2 [7:0][1:0][1:0];
wire [7:0] out1, out2;
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
end
endmodule
test/core/unpacked_array_depth.v 0 → 100644
module example(
input wire [7:0] inp,
output wire [7:0] out
);
assign out = ~inp;
endmodule
module top;
reg [7:0] arr1 [1:0];
reg [7:0] arr2 [1:0][1:0];
wire [7:0] out1, out2;
example e1(arr1[0], out1);
example e2(arr2[0][0], out2);
initial begin
#1 arr1[0] = 8'hAD;
#1 arr2[0][0] = 8'h42;
end
endmodule
test/core/unpacked_localparam.sv 0 → 100644
module top;
localparam logic [7:0] init_val [4] = {8'd0, 8'd8, 8'd10, 8'd200};
initial begin
integer i, j;
for (i = 0; i < 4; i += 1) begin
$display(init_val[i]);
for (j = 0; j < 8; j += 1) begin
$display(init_val[i][j]);
end
end
end
endmodule
test/core/unpacked_localparam.v 0 → 100644
module top;
localparam [31:0] init_val = {8'd0, 8'd8, 8'd10, 8'd200};
initial begin : foo
integer i, j;
for (i = 3; i >= 0; i -= 1) begin
$display(init_val[8*i+:8]);
for (j = 0; j < 8; j += 1) begin
$display(init_val[8*i+j]);
end
end
end
endmodule
test/core/unsigned.sv 0 → 100644
module top;
logic [3:0] arr;
initial
for (int unsigned i = 0; i < 4; i++)
arr[i] = i;
initial $display(arr);
parameter unsigned foo = 1;
localparam unsigned bar = 1;
initial $display(foo, bar);
endmodule
test/core/unsigned.v 0 → 100644
module top;
reg [3:0] arr;
initial begin : block_name
integer i;
for (i = 0; i < 4; i++)
arr[i] = i;
end
initial $display(arr);
parameter foo = 1;
localparam bar = 1;
initial $display(foo, bar);
endmodule
test/basic/package_self_reference_import.sv → test/core/unused_imports.sv
package Q;
localparam Bar = 1;
endpackage
package P; package P;
import Q::Bar; localparam FOO = 1;
localparam Foo = P::Bar; localparam BAR = 2;
endpackage endpackage
import P::*;
module top; module top;
import P::*; initial $display(FOO);
initial $display(Foo);
endmodule endmodule
test/core/unused_imports.v 0 → 100644
module top;
localparam FOO = 1;
initial $display(FOO);
endmodule
test/core/wire_reg.sv 0 → 100644
module top(inp, out);
input wire inp;
reg data;
always @* data = inp;
output logic [1:0] out;
parameter ON = 1;
generate
if (ON) begin : blk
assign out[0] = data;
always @* out[1] = data;
end
endgenerate
endmodule
test/core/wire_reg.v 0 → 100644
module top(inp, out);
input wire inp;
reg data;
always @* data = inp;
output reg [1:0] out;
parameter ON = 1;
generate
if (ON) begin : blk
always @* out[0] = data;
always @* out[1] = data;
end
endgenerate
endmodule
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