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lvzhengyang
sv2v
Commits
d2a18e01
Commit
d2a18e01
authored
Jun 03, 2021
by
Zachary Snow
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replace integer unsigned with size-32 reg
parent
36fcce89
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3 changed files
with
7 additions
and
5 deletions
+7
-5
src/Convert/Unsigned.hs
+2
-0
test/basic/typeof_signed.v
+3
-3
test/lib/functions.sh
+2
-2
No files found.
src/Convert/Unsigned.hs
View file @
d2a18e01
...
@@ -24,4 +24,6 @@ convertType :: Type -> Type
...
@@ -24,4 +24,6 @@ convertType :: Type -> Type
convertType
(
Implicit
Unsigned
rs
)
=
Implicit
Unspecified
rs
convertType
(
Implicit
Unsigned
rs
)
=
Implicit
Unspecified
rs
convertType
(
IntegerVector
t
Unsigned
rs
)
=
IntegerVector
t
Unspecified
rs
convertType
(
IntegerVector
t
Unsigned
rs
)
=
IntegerVector
t
Unspecified
rs
convertType
(
Net
t
Unsigned
rs
)
=
Net
t
Unspecified
rs
convertType
(
Net
t
Unsigned
rs
)
=
Net
t
Unspecified
rs
convertType
(
IntegerAtom
TInteger
Unsigned
)
=
IntegerVector
TReg
Unspecified
[(
RawNum
31
,
RawNum
0
)]
convertType
other
=
other
convertType
other
=
other
test/basic/typeof_signed.v
View file @
d2a18e01
`define
MAKE_PRIM
(
typ
,
base
,
size
)
\
`define
MAKE_PRIM
(
typ
,
base
,
size
)
\
base
[
size
-
1
:
0
]
typ
`
`_unspecified
=
1
;
\
base
[
size
-
1
:
0
]
typ
`
`_unspecified
=
1
;
\
base
unsigned
[
size
-
1
:
0
]
typ
`
`_unsigned
=
1
;
\
base
[
size
-
1
:
0
]
typ
`
`_unsigned
=
1
;
\
base
signed
[
size
-
1
:
0
]
typ
`
`_signed
=
1
;
base
signed
[
size
-
1
:
0
]
typ
`
`_signed
=
1
;
module
top
;
module
top
;
...
@@ -18,8 +18,8 @@ module top;
...
@@ -18,8 +18,8 @@ module top;
`MAKE_PRIM
(
shortint
,
reg
,
16
)
`MAKE_PRIM
(
shortint
,
reg
,
16
)
`MAKE_PRIM
(
int
,
reg
,
32
)
`MAKE_PRIM
(
int
,
reg
,
32
)
integer
integer_unspecified
=
1
;
integer
integer_unspecified
=
1
;
integer
unsigned
integer_unsigned
=
1
;
reg
[
31
:
0
]
integer_unsigned
=
1
;
integer
signed
integer_signed
=
1
;
integer
integer_signed
=
1
;
`MAKE_PRIM
(
longint
,
reg
,
64
)
`MAKE_PRIM
(
longint
,
reg
,
64
)
`MAKE_PRIM
(
bit
,
wire
,
1
)
`MAKE_PRIM
(
bit
,
wire
,
1
)
...
...
test/lib/functions.sh
View file @
d2a18e01
...
@@ -54,8 +54,8 @@ assertConverts() {
...
@@ -54,8 +54,8 @@ assertConverts() {
assertTrue
"2nd conversion of
$ac_file
failed"
$?
assertTrue
"2nd conversion of
$ac_file
failed"
$?
diff
$ac_tmpa
$ac_tmpb
>
/dev/null
diff
$ac_tmpa
$ac_tmpb
>
/dev/null
assertTrue
"conversion of
$ac_file
not stable after the first iteration"
$?
assertTrue
"conversion of
$ac_file
not stable after the first iteration"
$?
# using sed to remove quoted strings
and integer unsigned
# using sed to remove quoted strings
filtered
=
`
sed
-E
-e
's/"([^"]|\")+"//g'
-e
's/integer unsigned/integer
/g'
$ac_tmpa
`
filtered
=
`
sed
-E
's/"([^"]|\")+"/
/g'
$ac_tmpa
`
# check for various things iverilog accepts which we don't want to output
# check for various things iverilog accepts which we don't want to output
prefix
=
"conversion of
$ac_file
still contains"
prefix
=
"conversion of
$ac_file
still contains"
assertNotMatch
"
$filtered
"
"
$prefix
dimension queries"
\
assertNotMatch
"
$filtered
"
"
$prefix
dimension queries"
\
...
...
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