Commit c936b39b by Zachary Snow

use system functions for signedness casts

parent 06411d70
......@@ -31,6 +31,7 @@ import qualified Convert.NestPI
import qualified Convert.Package
import qualified Convert.ParamType
import qualified Convert.RemoveComments
import qualified Convert.SignCast
import qualified Convert.Simplify
import qualified Convert.SizeCast
import qualified Convert.StarPort
......@@ -72,6 +73,7 @@ phases excludes =
, Convert.Unique.convert
, Convert.UnpackedArray.convert
, Convert.Unsigned.convert
, Convert.SignCast.convert
, Convert.Package.convert
, Convert.Enum.convert
, Convert.NestPI.convert
......
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion for `signed` and `unsigned` type casts.
-
- SystemVerilog has `signed'(foo)` and `unsigned'(foo)` as syntactic sugar for
- the `$signed` and `$unsigned` system functions present in Verilog-2005. This
- conversion elaborates these casts.
-}
module Convert.SignCast (convert) where
import Convert.Traverse
import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
convert =
map $
traverseDescriptions $
traverseModuleItems $
traverseExprs $
traverseNestedExprs convertExpr
convertExpr :: Expr -> Expr
convertExpr (Cast (Left (Implicit Signed [])) e) =
Call (Ident "$signed") (Args [Just e] [])
convertExpr (Cast (Left (Implicit Unsigned [])) e) =
Call (Ident "$unsigned") (Args [Just e] [])
convertExpr other = other
......@@ -77,6 +77,7 @@ executable sv2v
Convert.Package
Convert.ParamType
Convert.RemoveComments
Convert.SignCast
Convert.Simplify
Convert.SizeCast
Convert.StarPort
......
module top;
initial begin
$display(signed'(4294967295));
$display(unsigned'(4294967295));
$display(signed'(-1));
$display(unsigned'(-1));
end
endmodule
module top;
initial begin
$display($signed(4294967295));
$display($unsigned(4294967295));
$display($signed(-1));
$display($unsigned(-1));
end
endmodule
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