allow time delay values

c722e931 · Zachary Snow · 1e35ba26 · c722e931
Commit c722e931 authored Oct 11, 2019 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+1 -4

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1030,13 +1030,10 @@ Sense :: { Sense }
 DelayValue :: { Expr }
  : Number { Number $1 }
+  | Time   { Time   $1 }
  | Identifier { Ident $1 }
  | Identifier "::" Identifier { PSIdent $1 $3 }
  | "(" Expr ":" Expr ":" Expr ")" { MinTypMax $2 $4 $6 }
-- TODO: Support these other DelayValues?
-- | real_number
-- | time_literal
-- | 1step
 CaseKW :: { CaseKW }
  : "case"  { CaseN }