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lvzhengyang
sv2v
Commits
c1f027e1
Commit
c1f027e1
authored
Nov 19, 2019
by
Zachary Snow
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$readmemh/$readmemb imply reg (resolves #57)
parent
58ad1fea
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src/Convert/Logic.hs
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src/Convert/Logic.hs
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c1f027e1
...
...
@@ -135,13 +135,20 @@ convertDescription ports orig =
convertDecl
other
=
other
regIdents
::
ModuleItem
->
Writer
Idents
()
regIdents
(
AlwaysC
_
stmt
)
=
regIdents
(
AlwaysC
_
stmt
)
=
do
collectNestedStmtsM
collectReadMemsM
stmt
collectNestedStmtsM
(
collectStmtLHSsM
(
collectNestedLHSsM
lhsIdents
))
$
traverseNestedStmts
removeTimings
stmt
where
removeTimings
::
Stmt
->
Stmt
removeTimings
(
Timing
_
s
)
=
s
removeTimings
other
=
other
collectReadMemsM
::
Stmt
->
Writer
Idents
()
collectReadMemsM
(
Subroutine
(
Ident
f
)
(
Args
(
_
:
Just
(
Ident
x
)
:
_
)
[]
))
=
if
f
==
"$readmemh"
||
f
==
"$readmemb"
then
tell
$
Set
.
singleton
x
else
return
()
collectReadMemsM
_
=
return
()
regIdents
(
Initial
stmt
)
=
regIdents
$
AlwaysC
Always
stmt
regIdents
(
Final
stmt
)
=
...
...
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