Fix compiliation; trailing whitespace; added .gitignore

.gitignore

+*.swp
+dist/

Data/BitVec.hs

@@ -8,6 +8,7 @@ module Data.BitVec
   ) where
 
 import Data.Bits
+import Data.Semigroup
 
 data BitVec = BitVec Int Integer deriving (Show, Eq)
 
@@ -39,6 +40,9 @@ instance Bits BitVec where
   isSigned _ = False
   popCount (BitVec _ v) = popCount v
 
+instance Semigroup BitVec where
+  (<>) = mappend
+
 instance Monoid BitVec where
   mempty = BitVec 0 0
   mappend (BitVec w1 v1) (BitVec w2 v2) = BitVec (w1 + w2) (shiftL v1 w2 .|. v2)

Language/Verilog/AST.hs

@@ -17,6 +17,7 @@ module Language.Verilog.AST
 import Data.Bits
 import Data.List
 import Data.Maybe
+import Data.Semigroup
 import Text.Printf
 
 import Data.BitVec
@@ -210,6 +211,8 @@ instance Bits Expr where
   bit          = error "Not supported: bit"
   popCount     = error "Not supported: popCount"
 
+instance Semigroup Expr where
+  (<>) = mappend
 
 instance Monoid Expr where
   mempty      = 0