allow empty list_of_parameter_assignments

bcafef8d · Zachary Snow · 279a19ab · bcafef8d
Commit bcafef8d authored Mar 30, 2020 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+2 -1

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -942,7 +942,8 @@ PortBinding :: { PortBinding }
  | ".*"                             { ("*", Nothing) }

 ParamBindings :: { [ParamBinding] }
-  : "#" "(" ParamBindingsInside ")" { $3 }
+  : "#" "("                     ")" { [] }
+  | "#" "(" ParamBindingsInside ")" { $3 }
 ParamBindingsInside :: { [ParamBinding] }
  : ParamBinding                         { [$1] }
  | ParamBinding "," ParamBindingsInside { $1 : $3}