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lvzhengyang
sv2v
Commits
ba270acb
Commit
ba270acb
authored
Apr 29, 2021
by
Zachary Snow
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forbid mixing ordered and named port or param bindings
parent
b0b79625
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3 changed files
with
37 additions
and
2 deletions
+37
-2
src/Language/SystemVerilog/Parser/Parse.y
+17
-2
test/error/binding_mix_param.sv
+11
-0
test/error/binding_mix_port.sv
+9
-0
No files found.
src/Language/SystemVerilog/Parser/Parse.y
View file @
ba270acb
...
...
@@ -966,7 +966,7 @@ LHSs :: { [LHS] }
PortBindings
::
{
[
PortBinding
]
}
:
"("
")"
{
[]
}
|
"("
PortBindingsInside
")"
{
$
2
}
|
"("
PortBindingsInside
")"
{
%
checkPortBindings
$
2
}
PortBindingsInside
::
{
[
PortBinding
]
}
:
PortBinding
opt
(
","
)
{
[
$
1
]
}
|
PortBinding
","
PortBindingsInside
{
$
1
:
$
3
}
...
...
@@ -978,7 +978,7 @@ PortBinding :: { PortBinding }
ParamBindings
::
{
[
ParamBinding
]
}
:
"#"
"("
")"
{
[]
}
|
"#"
"("
ParamBindingsInside
")"
{
$
3
}
|
"#"
"("
ParamBindingsInside
")"
{
%
checkParamBindings
$
3
}
ParamBindingsInside
::
{
[
ParamBinding
]
}
:
ParamBinding
opt
(
","
)
{
[
$
1
]
}
|
ParamBinding
","
ParamBindingsInside
{
$
1
:
$
3
}
...
...
@@ -1506,4 +1506,19 @@ missingToken expected = do
p
<-
gets
pPosition
throwError
$
show
p
++
": Parse error: missing expected `"
++
expected
++
"`"
checkPortBindings
::
[
PortBinding
]
->
ParseState
[
PortBinding
]
checkPortBindings
=
checkBindings
"port connections"
checkParamBindings
::
[
ParamBinding
]
->
ParseState
[
ParamBinding
]
checkParamBindings
=
checkBindings
"parameter overrides"
checkBindings
::
String
->
[(
Identifier
,
a
)]
->
ParseState
[(
Identifier
,
a
)]
checkBindings
kind
bindings
=
if
all
null
bindingNames
||
all
(
not
.
null
)
bindingNames
then
return
bindings
else
do
p
<-
gets
pPosition
error
$
show
p
++
": Parse error: illegal mix of ordered and named "
++
kind
where
bindingNames
=
map
fst
bindings
}
test/error/binding_mix_param.sv
0 → 100644
View file @
ba270acb
// pattern: illegal mix of ordered and named parameter overrides
module
example
#(
parameter
P
=
1
,
Q
=
2
)
(
input
a
,
b
,
c
)
;
endmodule
module
top
;
wire
a
,
b
,
c
;
example
#(
1
,
.
Q
(
2
))
e
(
.*
)
;
endmodule
test/error/binding_mix_port.sv
0 → 100644
View file @
ba270acb
// pattern: illegal mix of ordered and named port connections
module
example
(
input
a
,
b
,
c
)
;
endmodule
module
top
;
wire
a
,
b
,
c
;
example
e
(
1
,
.*
)
;
endmodule
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