diff --git a/src/Convert/DimensionQuery.hs b/src/Convert/DimensionQuery.hs
index 6e637f8..ade09a8 100644
--- a/src/Convert/DimensionQuery.hs
+++ b/src/Convert/DimensionQuery.hs
@@ -25,11 +25,7 @@ import Convert.Traverse
import Language.SystemVerilog.AST
convert :: [AST] -> [AST]
-convert files =
- if files == files'
- then files
- else convert files'
- where files' = map (traverseDescriptions convertDescription) files
+convert = map $ traverseDescriptions convertDescription
convertDescription :: Description -> Description
convertDescription =
diff --git a/src/Convert/NestPI.hs b/src/Convert/NestPI.hs
index 9bb5a89..1bf984d 100644
--- a/src/Convert/NestPI.hs
+++ b/src/Convert/NestPI.hs
@@ -21,15 +21,9 @@ convert =
map (filter (not . isPI)) . nest
where
nest :: [AST] -> [AST]
- nest curr =
- if next == curr
- then curr
- else nest next
- where
- next = traverseFiles
- (collectDescriptionsM collectDescriptionM)
- (traverseDescriptions . convertDescription)
- curr
+ nest = traverseFiles
+ (collectDescriptionsM collectDescriptionM)
+ (traverseDescriptions . convertDescription)
isPI :: Description -> Bool
isPI (PackageItem Import{}) = False
isPI (PackageItem item) = piName item /= Nothing
@@ -46,7 +40,9 @@ collectDescriptionM _ = return ()
-- nests packages items missing from modules
convertDescription :: PIs -> Description -> Description
convertDescription pis (orig @ Part{}) =
- Part attrs extern kw lifetime name ports items'
+ if Map.null pis
+ then orig
+ else Part attrs extern kw lifetime name ports items'
where
Part attrs extern kw lifetime name ports items = orig
items' = addItems pis Set.empty items
diff --git a/src/Convert/ParamType.hs b/src/Convert/ParamType.hs
index c832ea0..c2fa02a 100644
--- a/src/Convert/ParamType.hs
+++ b/src/Convert/ParamType.hs
@@ -233,7 +233,7 @@ convertModuleItemM info (orig @ (Instance m bindings x r p)) =
if Map.notMember m info then
return orig
else if Map.null maybeTypeMap then
- return $ Instance m bindingsNamed x r p
+ return orig
else if any (isLeft . snd) bindings' then
error $ "param type resolution left type params: " ++ show orig
++ " converted to: " ++ show bindings'
diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 4422334..0e545f9 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -80,11 +80,6 @@ instance Show Expr where
show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
show (Concat l ) = printf "{%s}" (commas $ map show l)
show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l)
- show (UniOp o e ) = printf "%s%s" (show o) (showUniOpPrec e)
- show (BinOp o a b) = printf "%s %s %s" (showBinOpPrec a) (show o) (showBinOpPrec b)
- show (Dot e n ) = printf "%s.%s" (show e) n
- show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
- show (Call e l ) = printf "%s%s" (show e) (show l)
show (Cast tore e ) = printf "%s'(%s)" (showEither tore) (show e)
show (DimsFn f v ) = printf "%s(%s)" (show f) (showEither v)
show (DimFn f v e) = printf "%s(%s, %s)" (show f) (showEither v) (show e)
@@ -99,6 +94,37 @@ instance Show Expr where
showPatternItem (':' : n, e) = showPatternItem (n, e)
showPatternItem (n , e) = printf "%s: %s" n (show e)
show (MinTypMax a b c) = printf "(%s : %s : %s)" (show a) (show b) (show c)
+ show (e @ UniOp{}) = showsPrec 0 e ""
+ show (e @ BinOp{}) = showsPrec 0 e ""
+ show (e @ Dot {}) = showsPrec 0 e ""
+ show (e @ Mux {}) = showsPrec 0 e ""
+ show (e @ Call {}) = showsPrec 0 e ""
+
+ showsPrec _ (UniOp o e ) =
+ shows o .
+ showUniOpPrec e
+ showsPrec _ (BinOp o a b) =
+ showBinOpPrec a .
+ showChar ' ' .
+ shows o .
+ showChar ' ' .
+ showBinOpPrec b
+ showsPrec _ (Dot e n ) =
+ shows e .
+ showChar '.' .
+ showString n
+ showsPrec _ (Mux c a b) =
+ showChar '(' .
+ shows c .
+ showString " ? " .
+ shows a .
+ showString " : " .
+ shows b .
+ showChar ')'
+ showsPrec _ (Call e l ) =
+ shows e .
+ shows l
+ showsPrec _ e = \s -> show e ++ s
data Args
= Args [Maybe Expr] [(Identifier, Maybe Expr)]
@@ -184,14 +210,14 @@ readNumber ('\'' : 'h' : rest) =
_ -> Nothing
readNumber n = readMaybe n
-showUniOpPrec :: Expr -> String
-showUniOpPrec (e @ UniOp{}) = printf "(%s)" (show e)
-showUniOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
-showUniOpPrec e = show e
+showUniOpPrec :: Expr -> ShowS
+showUniOpPrec (e @ UniOp{}) = (showParen True . shows) e
+showUniOpPrec (e @ BinOp{}) = (showParen True . shows) e
+showUniOpPrec e = shows e
-showBinOpPrec :: Expr -> String
-showBinOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
-showBinOpPrec e = show e
+showBinOpPrec :: Expr -> ShowS
+showBinOpPrec (e @ BinOp{}) = (showParen True . shows) e
+showBinOpPrec e = shows e
-- basic expression simplfication utility to help us generate nicer code in the
-- common case of ranges like `[FOO-1:0]`
diff --git a/src/Language/SystemVerilog/AST/ShowHelp.hs b/src/Language/SystemVerilog/AST/ShowHelp.hs
index 5fa255f..df35a0f 100644
--- a/src/Language/SystemVerilog/AST/ShowHelp.hs
+++ b/src/Language/SystemVerilog/AST/ShowHelp.hs
@@ -19,7 +19,7 @@ import Data.List (intercalate)
showPad :: Show t => t -> String
showPad x =
- if str == ""
+ if null str
then ""
else str ++ " "
where str = show x
@@ -28,14 +28,14 @@ showPadBefore :: Show t => t -> String
showPadBefore x =
if str == ""
then ""
- else " " ++ str
+ else ' ' : str
where str = show x
indent :: String -> String
-indent a = '\t' : f a
+indent = (:) '\t' . f
where
f [] = []
- f ('\n' : xs) = "\n\t" ++ f xs
+ f ('\n' : xs) = '\n' : '\t' : f xs
f (x : xs) = x : f xs
unlines' :: [String] -> String
@@ -46,7 +46,7 @@ commas = intercalate ", "
indentedParenList :: [String] -> String
indentedParenList [] = "()"
-indentedParenList [x] = "(" ++ x ++ ")"
+indentedParenList [x] = '(' : x ++ ")"
indentedParenList l = "(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
showEither :: (Show a, Show b) => Either a b -> String