Commit b124a561 by Zachary Snow

updated binary and unary operator printing (resolves #72)

parent aea64e90
...@@ -75,8 +75,8 @@ instance Show Expr where ...@@ -75,8 +75,8 @@ instance Show Expr where
show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l) show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
show (Concat l ) = printf "{%s}" (commas $ map show l) show (Concat l ) = printf "{%s}" (commas $ map show l)
show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l) show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l)
show (UniOp o e ) = printf "%s%s" (show o) (show e) show (UniOp o e ) = printf "%s%s" (show o) (showUniOpPrec e)
show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b) show (BinOp o a b) = printf "%s %s %s" (showBinOpPrec a) (show o) (showBinOpPrec b)
show (Dot e n ) = printf "%s.%s" (show e) n show (Dot e n ) = printf "%s.%s" (show e) n
show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b) show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
show (Call e l ) = printf "%s%s" (show e) (show l) show (Call e l ) = printf "%s%s" (show e) (show l)
...@@ -175,6 +175,15 @@ readNumber n = ...@@ -175,6 +175,15 @@ readNumber n =
'\'' : 'd' : rest -> rest '\'' : 'd' : rest -> rest
_ -> n _ -> n
showUniOpPrec :: Expr -> String
showUniOpPrec (e @ UniOp{}) = printf "(%s)" (show e)
showUniOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
showUniOpPrec e = show e
showBinOpPrec :: Expr -> String
showBinOpPrec (e @ BinOp{}) = printf "(%s)" (show e)
showBinOpPrec e = show e
-- basic expression simplfication utility to help us generate nicer code in the -- basic expression simplfication utility to help us generate nicer code in the
-- common case of ranges like `[FOO-1:0]` -- common case of ranges like `[FOO-1:0]`
simplify :: Expr -> Expr simplify :: Expr -> Expr
......
module Example(a, b);
input logic [1:0] a;
output logic b;
assign b = !(&a);
endmodule
module Example(a, b);
input wire [1:0] a;
output wire b;
assign b = !(&a);
endmodule
module top;
reg [1:0] a;
wire b;
Example example(a, b);
initial begin
$monitor("%2d %b %b", $time, a, b);
#1;
#1; a[0] = 1;
#1; a[1] = 1;
#1; a[0] = 1'sbx;
end
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment