Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
aea2975d
Commit
aea2975d
authored
Feb 19, 2021
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
remove outdated TODOs
parent
357b2921
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
4 additions
and
9 deletions
+4
-9
src/Convert/ParamType.hs
+0
-1
src/Language/SystemVerilog/AST/Decl.hs
+1
-3
test/basic/paramtype.sv
+2
-3
test/basic/struct_param.sv
+1
-2
No files found.
src/Convert/ParamType.hs
View file @
aea2975d
...
@@ -184,7 +184,6 @@ collectDescriptionM (part @ (Part _ _ _ _ name _ _)) =
...
@@ -184,7 +184,6 @@ collectDescriptionM (part @ (Part _ _ _ _ name _ _)) =
maybeTypeMap
=
Map
.
fromList
$
maybeTypeMap
=
Map
.
fromList
$
map
(
\
(
x
,
y
)
->
(
x
,
fromJust
y
))
$
map
(
\
(
x
,
y
)
->
(
x
,
fromJust
y
))
$
filter
(
isJust
.
snd
)
params
filter
(
isJust
.
snd
)
params
--- TODO FIXME XXX
collectDeclM
::
Decl
->
Writer
[(
Identifier
,
Maybe
(
Maybe
Type
))]
()
collectDeclM
::
Decl
->
Writer
[(
Identifier
,
Maybe
(
Maybe
Type
))]
()
collectDeclM
(
Param
Parameter
_
x
_
)
=
tell
[(
x
,
Nothing
)]
collectDeclM
(
Param
Parameter
_
x
_
)
=
tell
[(
x
,
Nothing
)]
collectDeclM
(
ParamType
Parameter
x
v
)
=
collectDeclM
(
ParamType
Parameter
x
v
)
=
...
...
src/Language/SystemVerilog/AST/Decl.hs
View file @
aea2975d
...
@@ -3,9 +3,7 @@
...
@@ -3,9 +3,7 @@
- Author: Zachary Snow <zach@zachjs.com>
- Author: Zachary Snow <zach@zachjs.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
-
-
- SystemVerilog data, net, and paramter declarations
- SystemVerilog data, net, and parameter declarations
-
- TODO: Normal parameters can be declared with no default value.
-}
-}
module
Language.SystemVerilog.AST.Decl
module
Language.SystemVerilog.AST.Decl
...
...
test/basic/paramtype.sv
View file @
aea2975d
...
@@ -52,12 +52,11 @@ module n_tdef #(
...
@@ -52,12 +52,11 @@ module n_tdef #(
end
end
endmodule
endmodule
// TODO Add support for parameters without default values.
module
o_nodef
#(
module
o_nodef
#(
parameter
a
=
0
,
parameter
a
,
parameter
type
T
,
parameter
type
T
,
parameter
type
U
,
parameter
type
U
,
parameter
b
=
0
parameter
b
)
;
)
;
T
x
=
a
;
T
x
=
a
;
U
y
=
b
;
U
y
=
b
;
...
...
test/basic/struct_param.sv
View file @
aea2975d
// TODO Add support for parameters without default values.
module
Module
#(
parameter
type
T
,
parameter
N
)
;
module
Module
#(
parameter
type
T
,
parameter
N
=
1
)
;
T
t
;
T
t
;
type
(
t
.
a
)
x
;
type
(
t
.
a
)
x
;
type
(
t
.
b
)
y
;
type
(
t
.
b
)
y
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment