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lvzhengyang
sv2v
Commits
aa429204
Commit
aa429204
authored
Jun 10, 2023
by
Zachary Snow
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minor AlwaysKW coverage improvements
parent
3db3fc0c
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5 changed files
with
25 additions
and
10 deletions
+25
-10
src/Convert/AlwaysKW.hs
+0
-1
test/core/always_sense.sv
+9
-2
test/core/always_sense.v
+9
-2
test/core/always_sense.vh
+2
-0
test/core/always_sense_tb.v
+5
-5
No files found.
src/Convert/AlwaysKW.hs
View file @
aa429204
...
...
@@ -212,7 +212,6 @@ ports = filter ((/= Local) . snd) . map port
port
::
Decl
->
PortDir
port
(
Variable
d
_
x
_
_
)
=
(
x
,
d
)
port
(
Net
d
_
_
_
x
_
_
)
=
(
x
,
d
)
port
_
=
(
""
,
Local
)
-- get a list of non-local variables referenced within a module item, and
...
...
test/core/always_sense.sv
View file @
aa429204
`include
"always_sense.vh"
module
mod
(
input
wire
inp1
,
inp2
,
output
reg
out1
,
out2
,
out3
,
out4
,
out5
,
out6
,
out7
,
out8
,
out9
,
outA
,
outB
input
wire
`INPUTS
,
output
reg
`OUTPUTS
)
;
localparam
ZERO
=
0
;
...
...
@@ -75,4 +76,10 @@ module mod(
endfunction
always_comb
outB
=
h
(
ZERO
)
;
function
automatic
i
;
input
reg
x
;
// ignored
i
=
s
[
ONE
]
;
endfunction
always_comb
asgn
(
.
i
(
i
(
ZERO
))
,
.
o
(
outC
))
;
endmodule
test/core/always_sense.v
View file @
aa429204
`include
"always_sense.vh"
module
mod
(
input
wire
inp1
,
inp2
,
output
reg
out1
,
out2
,
out3
,
out4
,
out5
,
out6
,
out7
,
out8
,
out9
,
outA
,
outB
input
wire
`INPUTS
,
output
reg
`OUTPUTS
)
;
localparam
ZERO
=
0
;
...
...
@@ -73,4 +74,10 @@ module mod(
endfunction
always
@
(
s
[
0
])
outB
=
h
(
ZERO
)
;
function
automatic
i
;
input
reg
x
;
// ignored
i
=
s
[
1
]
;
endfunction
always
@
(
s
[
1
])
asgn
(
outC
,
i
(
ZERO
))
;
endmodule
test/core/always_sense.vh
0 → 100644
View file @
aa429204
`define INPUTS inp1, inp2
`define OUTPUTS out1, out2, out3, out4, out5, out6, out7, out8, out9, outA, outB, outC
test/core/always_sense_tb.v
View file @
aa429204
`include
"always_sense.vh"
module
top
;
reg
inp1
,
inp2
;
wire
out1
,
out2
,
out3
,
out4
,
out5
,
out6
,
out7
,
out8
,
out9
,
outA
,
outB
;
mod
m
(
inp1
,
inp2
,
out1
,
out2
,
out3
,
out4
,
out5
,
out6
,
out7
,
out8
,
out9
,
outA
,
outB
)
;
reg
`INPUTS
;
wire
`OUTPUTS
;
mod
m
(
`INPUTS
,
`OUTPUTS
)
;
initial
begin
$
monitor
(
inp1
,
inp2
,
out1
,
out2
,
out3
,
out4
,
out5
,
out6
,
out7
,
out8
,
out9
,
outA
,
outB
)
;
$
monitor
(
`INPUTS
,
`OUTPUTS
)
;
repeat
(
2
)
begin
#
1
inp1
=
0
;
#
1
inp2
=
0
;
...
...
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