Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
a54be8da
Commit
a54be8da
authored
Jul 17, 2022
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
instances supply names during reordering
parent
59b416f9
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
65 additions
and
1 deletions
+65
-1
CHANGELOG.md
+1
-0
src/Convert/Package.hs
+5
-1
test/core/reorder_shadow.sv
+29
-0
test/core/reorder_shadow.v
+30
-0
No files found.
CHANGELOG.md
View file @
a54be8da
...
@@ -38,6 +38,7 @@
...
@@ -38,6 +38,7 @@
accessed directly
accessed directly
*
Fixed conversion of casts using structs containing multi-dimensional fields
*
Fixed conversion of casts using structs containing multi-dimensional fields
*
Fixed incorrect name resolution conflicts raised during interface inlining
*
Fixed incorrect name resolution conflicts raised during interface inlining
*
Fixed handling of interface instances which shadow other declarations
## v0.0.9
## v0.0.9
...
...
src/Convert/Package.hs
View file @
a54be8da
...
@@ -652,7 +652,7 @@ reorderGenItem item = item
...
@@ -652,7 +652,7 @@ reorderGenItem item = item
-- iteratively inserts missing package items exactly where they are needed
-- iteratively inserts missing package items exactly where they are needed
addItems
::
PIs
->
Idents
->
[(
ModuleItem
,
Idents
)]
->
[
ModuleItem
]
addItems
::
PIs
->
Idents
->
[(
ModuleItem
,
Idents
)]
->
[
ModuleItem
]
addItems
pis
existingPIs
((
item
,
usedPIs
)
:
items
)
=
addItems
pis
existingPIs
((
item
,
usedPIs
)
:
items
)
=
if
not
$
Set
.
disjoint
existingPIs
thisPI
then
if
not
$
forceKeep
||
Set
.
disjoint
existingPIs
thisPI
then
-- this item was re-imported earlier in the module
-- this item was re-imported earlier in the module
addItems
pis
existingPIs
items
addItems
pis
existingPIs
items
else
if
Map
.
null
itemsToAdd
then
else
if
Map
.
null
itemsToAdd
then
...
@@ -666,7 +666,11 @@ addItems pis existingPIs ((item, usedPIs) : items) =
...
@@ -666,7 +666,11 @@ addItems pis existingPIs ((item, usedPIs) : items) =
thisPI
=
case
item
of
thisPI
=
case
item
of
MIPackageItem
packageItem
->
MIPackageItem
packageItem
->
Set
.
fromList
$
piNames
packageItem
Set
.
fromList
$
piNames
packageItem
Instance
_
_
x
_
_
->
Set
.
singleton
x
_
->
Set
.
empty
_
->
Set
.
empty
forceKeep
=
case
item
of
Instance
{}
->
True
_
->
False
neededPIs
=
Set
.
difference
(
Set
.
difference
usedPIs
existingPIs
)
thisPI
neededPIs
=
Set
.
difference
(
Set
.
difference
usedPIs
existingPIs
)
thisPI
itemsToAdd
=
Map
.
restrictKeys
pis
neededPIs
itemsToAdd
=
Map
.
restrictKeys
pis
neededPIs
(
chosenName
,
chosenPI
)
=
Map
.
findMin
itemsToAdd
(
chosenName
,
chosenPI
)
=
Map
.
findMin
itemsToAdd
...
...
test/core/reorder_shadow.sv
0 → 100644
View file @
a54be8da
typedef
logic
over
;
interface
intf
;
logic
[
3
:
0
]
x
;
assign
x
[
0
]
=
0
;
initial
$
display
(
"intf x %b"
,
x
)
;
endinterface
module
mod
(
intf
i
)
;
assign
i
.
x
[
1
]
=
1
;
initial
$
display
(
"mod i.x %b"
,
i
.
x
)
;
endmodule
module
check
;
over
y
;
intf
over
()
;
mod
m
(
over
)
;
assign
over
.
x
[
2
]
=
1'bz
;
initial
$
display
(
"check over.x %b"
,
over
.
x
)
;
initial
$
display
(
"check y %b"
,
y
)
;
endmodule
module
top
;
check
c
()
;
intf
over
()
;
mod
m
(
over
)
;
assign
over
.
x
[
2
]
=
1'bz
;
initial
$
display
(
"top over.x %b"
,
over
.
x
)
;
endmodule
test/core/reorder_shadow.v
0 → 100644
View file @
a54be8da
module
check
;
wire
y
;
if
(
1
)
begin
:
over
wire
[
3
:
0
]
x
;
assign
x
[
0
]
=
0
;
initial
$
display
(
"intf x %b"
,
x
)
;
end
if
(
1
)
begin
:
m
assign
over
.
x
[
1
]
=
1
;
initial
$
display
(
"mod i.x %b"
,
over
.
x
)
;
end
assign
over
.
x
[
2
]
=
1'bz
;
initial
$
display
(
"check over.x %b"
,
over
.
x
)
;
initial
$
display
(
"check y %b"
,
y
)
;
endmodule
module
top
;
check
c
()
;
if
(
1
)
begin
:
over
wire
[
3
:
0
]
x
;
assign
x
[
0
]
=
0
;
initial
$
display
(
"intf x %b"
,
x
)
;
end
if
(
1
)
begin
:
m
assign
over
.
x
[
1
]
=
1
;
initial
$
display
(
"mod i.x %b"
,
over
.
x
)
;
end
assign
over
.
x
[
2
]
=
1'bz
;
initial
$
display
(
"top over.x %b"
,
over
.
x
)
;
endmodule
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment