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Commit a432d759 by Zachary Snow
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additional SystemVerilog language support 

- unique0 and priority
- uniqueness on if statements
- preliminary discard-only parsing of assertions
- parameters with alias typenames
parent 17fd6f8c
Showing with 237 additions and 26 deletions
src/Convert/Traverse.hs
......@@ -150,10 +150,10 @@ traverseNestedStmtsM mapper = fullMapper
cs (RepeatL e stmt) = fullMapper stmt >>= return . RepeatL e
cs (DoWhile e stmt) = fullMapper stmt >>= return . DoWhile e
cs (Forever stmt) = fullMapper stmt >>= return . Forever
cs (If e s1 s2) = do
cs (If u e s1 s2) = do
s1' <- fullMapper s1
s2' <- fullMapper s2
return $ If e s1' s2'
return $ If u e s1' s2'
cs (Timing event stmt) = fullMapper stmt >>= return . Timing event
cs (Return expr) = return $ Return expr
cs (Subroutine f exprs) = return $ Subroutine f exprs
......@@ -294,8 +294,8 @@ traverseExprsM mapper = moduleItemMapper
flatStmtMapper (DoWhile e stmt) =
exprMapper e >>= \e' -> return $ DoWhile e' stmt
flatStmtMapper (Forever stmt) = return $ Forever stmt
flatStmtMapper (If cc s1 s2) =
exprMapper cc >>= \cc' -> return $ If cc' s1 s2
flatStmtMapper (If u cc s1 s2) =
exprMapper cc >>= \cc' -> return $ If u cc' s1 s2
flatStmtMapper (Timing event stmt) = return $ Timing event stmt
flatStmtMapper (Subroutine f exprs) =
mapM maybeExprMapper exprs >>= return . Subroutine f
......
src/Convert/Unique.hs
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion for `unique`
- Conversion for `unique`, `unique0`, and `priority`
-
- This conversion simply drops the `unique` keyword, as it is only used for
- This conversion simply drops the keywords, as it is only used for
- optimization. There is no way to force toolchains which don't support the
- keyword to perform such optimization.
-}
......@@ -17,6 +17,8 @@ convert :: AST -> AST
convert = traverseDescriptions $ traverseModuleItems $ traverseStmts convertStmt
convertStmt :: Stmt -> Stmt
convertStmt (Case True kw expr cases def) =
Case False kw expr cases def
convertStmt (If (Just _) cc s1 s2) =
If Nothing cc s1 s2
convertStmt (Case (Just _) kw expr cases def) =
Case Nothing kw expr cases def
convertStmt other = other
src/Language/SystemVerilog/AST.hs
......@@ -128,6 +128,8 @@ data ModuleItem
| MIPackageItem PackageItem
| NInputGate NInputGateKW (Maybe Identifier) LHS [Expr]
| NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr
-- TODO: Should we support coversion of assertions?
-- | AssertionItem AssertionItem
deriving Eq
data AlwaysKW
......@@ -165,6 +167,7 @@ instance Show ModuleItem where
MIPackageItem i -> show i
NInputGate kw x lhs exprs -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs)
NOutputGate kw x lhss expr -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr)
--AssertionItem a -> show a
where
showPorts :: [PortBinding] -> String
showPorts ports = indentedParenList $ map showPort ports
......
src/Language/SystemVerilog/AST/Stmt.hs
......@@ -11,6 +11,15 @@ module Language.SystemVerilog.AST.Stmt
, Sense (..)
, CaseKW (..)
, Case
, ActionBlock (..)
, PropertyExpr (..)
, PESPBinOp (..)
, SeqMatchItem
, SeqExpr (..)
, AssertionItem
, Assertion (..)
, PropertySpec (..)
, UniquePriority (..)
) where
import Text.Printf (printf)
......@@ -26,7 +35,7 @@ import Language.SystemVerilog.AST.Type (Identifier)
data Stmt
= StmtAttr Attr Stmt
| Block (Maybe Identifier) [Decl] [Stmt]
| Case Bool CaseKW Expr [Case] (Maybe Stmt)
| Case (Maybe UniquePriority) CaseKW Expr [Case] (Maybe Stmt)
| For [Either Decl (LHS, Expr)] (Maybe Expr) [(LHS, AsgnOp, Expr)] Stmt
| AsgnBlk AsgnOp LHS Expr
| Asgn (Maybe Timing) LHS Expr
......@@ -34,11 +43,13 @@ data Stmt
| RepeatL Expr Stmt
| DoWhile Expr Stmt
| Forever Stmt
| If Expr Stmt Stmt
| If (Maybe UniquePriority) Expr Stmt Stmt
| Timing Timing Stmt
| Return Expr
| Subroutine Identifier [Maybe Expr]
| Trigger Identifier
-- TODO: Should we support coversion of assertions?
-- | Assertion Assertion
| Null
deriving Eq
......@@ -51,9 +62,8 @@ instance Show Stmt where
bodyLines = (map show decls) ++ (map show stmts)
body = indent $ unlines' bodyLines
show (Case u kw e cs def) =
printf "%s%s (%s)\n%s%s\nendcase" uniqStr (show kw) (show e) bodyStr defStr
printf "%s%s (%s)\n%s%s\nendcase" (maybe "" showPad u) (show kw) (show e) bodyStr defStr
where
uniqStr = if u then "unique " else ""
bodyStr = indent $ unlines' $ map showCase cs
defStr = case def of
Nothing -> ""
......@@ -77,11 +87,12 @@ instance Show Stmt where
show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
show (Forever s ) = printf "forever %s" (show s)
show (If a b Null) = printf "if (%s) %s" (show a) (show b)
show (If a b c ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
show (If u a b Null) = printf "%sif (%s) %s" (maybe "" showPad u) (show a) (show b)
show (If u a b c ) = printf "%sif (%s) %s\nelse %s" (maybe "" showPad u) (show a) (show b) (show c)
show (Return e ) = printf "return %s;" (show e)
show (Timing t s ) = printf "%s %s" (show t) (show s)
show (Trigger x ) = printf "-> %s;" x
--show (Assertion a) = show a
show (Null ) = ";"
data CaseKW
......@@ -122,3 +133,85 @@ instance Show Sense where
show (SensePosedge a ) = printf "posedge %s" (show a)
show (SenseNegedge a ) = printf "negedge %s" (show a)
show (SenseStar ) = "*"
data ActionBlock
= ActionBlockIf Stmt
| ActionBlockElse (Maybe Stmt) Stmt
deriving Eq
instance Show ActionBlock where
show (ActionBlockIf Null ) = ";"
show (ActionBlockIf s ) = printf " %s" (show s)
show (ActionBlockElse Nothing s ) = printf " else %s" (show s)
show (ActionBlockElse (Just s1) s2) = printf " %s else %s" (show s1) (show s2)
data PropertyExpr
= PESE SeqExpr
| PESPBinOp SeqExpr PESPBinOp PropertyExpr
deriving Eq
instance Show PropertyExpr where
show (PESE se) = show se
show (PESPBinOp a o b) = printf "(%s %s %s)" (show a) (show o) (show b)
data PESPBinOp
= ImpliesO
| ImpliesNO
| FollowedByO
| FollowedByNO
deriving (Eq, Ord)
instance Show PESPBinOp where
show ImpliesO = "|->"
show ImpliesNO = "|=>"
show FollowedByO = "#-#"
show FollowedByNO = "#=#"
type SeqMatchItem = Either (LHS, AsgnOp, Expr) (Identifier, [Maybe Expr])
data SeqExpr
= SeqExpr Expr
| SeqExprAnd SeqExpr SeqExpr
| SeqExprOr SeqExpr SeqExpr
| SeqExprIntersect SeqExpr SeqExpr
| SeqExprThroughout Expr SeqExpr
| SeqExprWithin SeqExpr SeqExpr
| SeqExprDelay (Maybe SeqExpr) Expr SeqExpr
| SeqExprFirstMatch SeqExpr [SeqMatchItem]
deriving Eq
instance Show SeqExpr where
show (SeqExpr a ) = show a
show (SeqExprAnd a b) = printf "(%s %s %s)" (show a) "and" (show b)
show (SeqExprOr a b) = printf "(%s %s %s)" (show a) "or" (show b)
show (SeqExprIntersect a b) = printf "(%s %s %s)" (show a) "intersect" (show b)
show (SeqExprThroughout a b) = printf "(%s %s %s)" (show a) "throughout" (show b)
show (SeqExprWithin a b) = printf "(%s %s %s)" (show a) "within" (show b)
show (SeqExprDelay me e s) = printf "%s##%s %s" (maybe "" showPad me) (show e) (show s)
show (SeqExprFirstMatch e l) = printf "first_match(%s, %s)" (show e) (commas $ map show l)
type AssertionItem = (Maybe Identifier, Assertion)
data Assertion
= Assert Expr ActionBlock
| AssertProperty PropertySpec ActionBlock
deriving Eq
instance Show Assertion where
show (Assert e a) =
printf "assert (%s)%s" (show e) (show a)
show (AssertProperty p a) =
printf "assert property (%s)%s" (show p) (show a)
data PropertySpec
= PropertySpec (Maybe Sense) (Maybe Expr) PropertyExpr
deriving Eq
instance Show PropertySpec where
show (PropertySpec ms me pe) =
printf "%s%s%s" (maybe "" showPad ms) meStr (show pe)
where
meStr = case me of
Nothing -> ""
Just e -> printf "disable iff (%s) " (show e)
data UniquePriority
= Unique
| Unique0
| Priority
deriving Eq
instance Show UniquePriority where
show Unique = "unique"
show Unique0 = "unique0"
show Priority = "priority"
src/Language/SystemVerilog/Parser/Lex.x
......@@ -107,6 +107,7 @@ tokens :-
"always_ff" { tok KW_always_ff }
"always_latch" { tok KW_always_latch }
"and" { tok KW_and }
"assert" { tok KW_assert }
"assign" { tok KW_assign }
"automatic" { tok KW_automatic }
"begin" { tok KW_begin }
......@@ -118,6 +119,7 @@ tokens :-
"casez" { tok KW_casez }
"default" { tok KW_default }
"defparam" { tok KW_defparam }
"disable" { tok KW_disable }
"do" { tok KW_do }
"else" { tok KW_else }
"end" { tok KW_end }
......@@ -129,18 +131,21 @@ tokens :-
"endtask" { tok KW_endtask }
"enum" { tok KW_enum }
"extern" { tok KW_extern }
"first_match" { tok KW_first_match }
"for" { tok KW_for }
"forever" { tok KW_forever }
"function" { tok KW_function }
"generate" { tok KW_generate }
"genvar" { tok KW_genvar }
"if" { tok KW_if }
"iff" { tok KW_iff }
"initial" { tok KW_initial }
"inout" { tok KW_inout }
"input" { tok KW_input }
"int" { tok KW_int }
"integer" { tok KW_integer }
"interface" { tok KW_interface }
"intersect" { tok KW_intersect }
"localparam" { tok KW_localparam }
"logic" { tok KW_logic }
"longint" { tok KW_longint }
......@@ -155,6 +160,8 @@ tokens :-
"packed" { tok KW_packed }
"parameter" { tok KW_parameter }
"posedge" { tok KW_posedge }
"priority" { tok KW_priority }
"property" { tok KW_property }
"real" { tok KW_real }
"realtime" { tok KW_realtime }
"reg" { tok KW_reg }
......@@ -168,6 +175,7 @@ tokens :-
"supply0" { tok KW_supply0 }
"supply1" { tok KW_supply1 }
"task" { tok KW_task }
"throughout" { tok KW_throughout }
"time" { tok KW_time }
"tri" { tok KW_tri }
"tri0" { tok KW_tri0 }
......@@ -177,11 +185,13 @@ tokens :-
"trireg" { tok KW_trireg }
"typedef" { tok KW_typedef }
"unique" { tok KW_unique }
"unique0" { tok KW_unique0 }
"unsigned" { tok KW_unsigned }
"uwire" { tok KW_uwire }
"wand" { tok KW_wand }
"while" { tok KW_while }
"wire" { tok KW_wire }
"within" { tok KW_within }
"wor" { tok KW_wor }
"xnor" { tok KW_xnor }
"xor" { tok KW_xor }
......@@ -272,6 +282,8 @@ tokens :-
"|->" { tok Sym_bar_dash_gt }
"|=>" { tok Sym_bar_eq_gt }
"[->" { tok Sym_brack_l_dash_gt }
"#-#" { tok Sym_pound_dash_pound }
"#=#" { tok Sym_pound_eq_pound }
"@@(" { tok Sym_at_at_paren_l }
"(*)" { tok Sym_paren_l_aster_paren_r }
"->>" { tok Sym_dash_gt_gt }
......
src/Language/SystemVerilog/Parser/Parse.y
......@@ -22,6 +22,7 @@ import Language.SystemVerilog.Parser.Tokens
"always_ff" { Token KW_always_ff _ _ }
"always_latch" { Token KW_always_latch _ _ }
"and" { Token KW_and _ _ }
"assert" { Token KW_assert _ _ }
"assign" { Token KW_assign _ _ }
"automatic" { Token KW_automatic _ _ }
"begin" { Token KW_begin _ _ }
......@@ -33,6 +34,7 @@ import Language.SystemVerilog.Parser.Tokens
"casez" { Token KW_casez _ _ }
"default" { Token KW_default _ _ }
"defparam" { Token KW_defparam _ _ }
"disable" { Token KW_disable _ _ }
"do" { Token KW_do _ _ }
"else" { Token KW_else _ _ }
"end" { Token KW_end _ _ }
......@@ -44,18 +46,21 @@ import Language.SystemVerilog.Parser.Tokens
"endtask" { Token KW_endtask _ _ }
"enum" { Token KW_enum _ _ }
"extern" { Token KW_extern _ _ }
"first_match" { Token KW_first_match _ _ }
"for" { Token KW_for _ _ }
"forever" { Token KW_forever _ _ }
"function" { Token KW_function _ _ }
"generate" { Token KW_generate _ _ }
"genvar" { Token KW_genvar _ _ }
"if" { Token KW_if _ _ }
"iff" { Token KW_iff _ _ }
"initial" { Token KW_initial _ _ }
"inout" { Token KW_inout _ _ }
"input" { Token KW_input _ _ }
"int" { Token KW_int _ _ }
"integer" { Token KW_integer _ _ }
"interface" { Token KW_interface _ _ }
"intersect" { Token KW_intersect _ _ }
"localparam" { Token KW_localparam _ _ }
"logic" { Token KW_logic _ _ }
"longint" { Token KW_longint _ _ }
......@@ -70,6 +75,8 @@ import Language.SystemVerilog.Parser.Tokens
"packed" { Token KW_packed _ _ }
"parameter" { Token KW_parameter _ _ }
"posedge" { Token KW_posedge _ _ }
"priority" { Token KW_priority _ _ }
"property" { Token KW_property _ _ }
"real" { Token KW_real _ _ }
"realtime" { Token KW_realtime _ _ }
"reg" { Token KW_reg _ _ }
......@@ -83,6 +90,7 @@ import Language.SystemVerilog.Parser.Tokens
"supply0" { Token KW_supply0 _ _ }
"supply1" { Token KW_supply1 _ _ }
"task" { Token KW_task _ _ }
"throughout" { Token KW_throughout _ _ }
"time" { Token KW_time _ _ }
"tri" { Token KW_tri _ _ }
"tri0" { Token KW_tri0 _ _ }
......@@ -92,11 +100,13 @@ import Language.SystemVerilog.Parser.Tokens
"trireg" { Token KW_trireg _ _ }
"typedef" { Token KW_typedef _ _ }
"unique" { Token KW_unique _ _ }
"unique0" { Token KW_unique0 _ _ }
"unsigned" { Token KW_unsigned _ _ }
"uwire" { Token KW_uwire _ _ }
"wand" { Token KW_wand _ _ }
"while" { Token KW_while _ _ }
"wire" { Token KW_wire _ _ }
"within" { Token KW_within _ _ }
"wor" { Token KW_wor _ _ }
"xnor" { Token KW_xnor _ _ }
"xor" { Token KW_xor _ _ }
......@@ -184,6 +194,8 @@ string { Token Lit_string _ _ }
"|->" { Token Sym_bar_dash_gt _ _ }
"|=>" { Token Sym_bar_eq_gt _ _ }
"[->" { Token Sym_brack_l_dash_gt _ _ }
"#-#" { Token Sym_pound_dash_pound _ _ }
"#=#" { Token Sym_pound_eq_pound _ _ }
"@@(" { Token Sym_at_at_paren_l _ _ }
"(*)" { Token Sym_paren_l_aster_paren_r _ _ }
"->>" { Token Sym_dash_gt_gt _ _ }
......@@ -196,6 +208,15 @@ directive { Token Spe_Directive _ _ }
-- operator precedences, from *lowest* to *highest*
%nonassoc NoElse
%nonassoc "else"
%right "|->" "|=>" "#-#" "#=#"
%right "iff"
%left "or"
%left "and"
%left "intersect"
%left "within"
%right "throughout"
%left "##"
%nonassoc "[*]" "[=]" "[->]"
%right "?" ":"
%left "||"
%left "&&"
......@@ -316,7 +337,9 @@ ParamDecls :: { [ModuleItem] }
: ParamDecl(")") { $1 }
| ParamDecl(",") ParamDecls { $1 ++ $2 }
ParamDecl(delim) :: { [ModuleItem] }
: "parameter" ParamType DeclAsgns delim { map (MIDecl . (uncurry $ Parameter $2)) $3 }
: ParameterDecl(OnlyParamKW, delim) { map MIDecl $1 }
OnlyParamKW :: { Type -> Identifier -> Expr -> Decl }
: "parameter" { Parameter }
PortDecls :: { ([Identifier], [ModuleItem]) }
: "(" DeclTokens(")") { parseDTsAsPortDecls $2 }
......@@ -400,8 +423,7 @@ ModuleItems :: { [ModuleItem] }
ModuleItem :: { [ModuleItem] }
-- This item covers module instantiations and all declarations
: DeclTokens(";") { parseDTsAsModuleItems $1 }
| "parameter" ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Parameter $2) $3 }
| "localparam" ParamType DeclAsgns ";" { map MIDecl $ map (uncurry $ Localparam $2) $3 }
| ParameterDecl(ParameterDeclKW, ";") { map MIDecl $1 }
| "defparam" DefparamAsgns ";" { map (uncurry Defparam) $2 }
| "assign" opt(DelayControl) LHS "=" Expr ";" { [Assign $2 $3 $5] }
| AlwaysKW Stmt { [AlwaysC $1 $2] }
......@@ -413,6 +435,67 @@ ModuleItem :: { [ModuleItem] }
| NInputGateKW NInputGates ";" { map (\(a, b, c) -> NInputGate $1 a b c) $2 }
| NOutputGateKW NOutputGates ";" { map (\(a, b, c) -> NOutputGate $1 a b c) $2 }
| AttributeInstance ModuleItem { map (MIAttr $1) $2 }
| AssertionItem { [] } -- AssertionItem $1] }
-- for ModuleItem, for now
AssertionItem :: { AssertionItem }
: ConcurrentAssertionItem { $1 }
-- for Stmt, for now
ProceduralAssertionStatement :: { Assertion }
: ConcurrentAssertionStatement { $1 }
| ImmediateAssertionStatement { $1 }
ConcurrentAssertionItem :: { AssertionItem }
: Identifier ":" ConcurrentAssertionStatement { (Just $1, $3) }
| ConcurrentAssertionStatement { (Nothing, $1) }
ConcurrentAssertionStatement :: { Assertion }
: "assert" "property" "(" PropertySpec ")" ActionBlock { AssertProperty $4 $6 }
-- TODO: Add support for assume, cover, and restrict
ImmediateAssertionStatement :: { Assertion }
: SimpleImmediateAssertionStatement { $1 }
SimpleImmediateAssertionStatement :: { Assertion }
: "assert" "(" Expr ")" ActionBlock { Assert $3 $5 }
-- TODO: Add support for assume and cover
PropertySpec :: { PropertySpec }
: opt(ClockingEvent) "disable" "iff" "(" Expr ")" PropertyExpr { PropertySpec $1 (Just $5) $7 }
| opt(ClockingEvent) PropertyExpr { PropertySpec $1 (Nothing) $2 }
-- TODO: This is pretty incomplete!
PropertyExpr :: { PropertyExpr }
: SeqExpr { PESE $1 }
| SeqExpr PESPBinOp PropertyExpr { PESPBinOp $1 $2 $3 }
-- | "(" PropertyExpr ")" { [] }
PESPBinOp :: { PESPBinOp }
: "|->" { ImpliesO }
| "|=>" { ImpliesNO }
| "#-#" { FollowedByO }
| "#=#" { FollowedByNO }
SeqExpr :: { SeqExpr }
: Expr { SeqExpr $1 }
| SeqExpr "and" SeqExpr { SeqExprAnd $1 $3 }
| SeqExpr "or" SeqExpr { SeqExprOr $1 $3 }
| SeqExpr "intersect" SeqExpr { SeqExprIntersect $1 $3 }
| Expr "throughout" SeqExpr { SeqExprThroughout $1 $3 }
| SeqExpr "within" SeqExpr { SeqExprWithin $1 $3 }
| SeqExpr "##" Number SeqExpr { SeqExprDelay (Just $1) (Number $3) $4 }
| "##" Number SeqExpr { SeqExprDelay (Nothing) (Number $2) $3 }
| "first_match" "(" SeqExpr SeqMatchItems ")" { SeqExprFirstMatch $3 $4 }
SeqMatchItems :: { [SeqMatchItem] }
: "," SeqMatchItem { [$2] }
| SeqMatchItems "," SeqMatchItem { $1 ++ [$3] }
SeqMatchItem :: { SeqMatchItem }
: ForStepAssignment { Left $1 }
| Identifier "(" CallArgs ")" { Right ($1, $3) }
ActionBlock :: { ActionBlock }
: Stmt %prec NoElse { ActionBlockIf $1 }
| "else" Stmt { ActionBlockElse (Nothing) $2 }
| Stmt "else" Stmt { ActionBlockElse (Just $1) $3 }
AttributeInstance :: { Attr }
: "(*" AttrSpecs "*)" { Attr $2 }
......@@ -487,7 +570,7 @@ TFItems :: { [Decl] }
ParamType :: { Type }
: "integer" Signing { IntegerAtom TInteger $2 }
| "integer" { IntegerAtom TInteger Unspecified }
| Dimensions { Implicit Unspecified $1 }
| DimensionsNonEmpty { Implicit Unspecified $1 }
| Signing Dimensions { Implicit $1 $2 }
Dimensions :: { [Range] }
......@@ -549,8 +632,8 @@ Stmt :: { Stmt }
StmtNonAsgn :: { Stmt }
: ";" { Null }
| "begin" opt(Tag) DeclsAndStmts "end" opt(Tag) { Block (combineTags $2 $5) (fst $3) (snd $3) }
| "if" "(" Expr ")" Stmt "else" Stmt { If $3 $5 $7 }
| "if" "(" Expr ")" Stmt %prec NoElse { If $3 $5 Null }
| Unique "if" "(" Expr ")" Stmt "else" Stmt { If $1 $4 $6 $8 }
| Unique "if" "(" Expr ")" Stmt %prec NoElse { If $1 $4 $6 Null }
| "for" "(" DeclTokens(";") opt(Expr) ";" ForStep ")" Stmt { For (parseDTsAsDeclsAndAsgns $3) $4 $6 $8 }
| Unique CaseKW "(" Expr ")" Cases opt(CaseDefault) "endcase" { Case $1 $2 $4 $6 $7 }
| TimingControl Stmt { Timing $1 $2 }
......@@ -562,6 +645,13 @@ StmtNonAsgn :: { Stmt }
| "forever" Stmt { Forever $2 }
| "->" Identifier ";" { Trigger $2 }
| AttributeInstance Stmt { StmtAttr $1 $2 }
| ProceduralAssertionStatement { Null } --Assertion $1 }
Unique :: { Maybe UniquePriority }
: {- empty -} { Nothing }
| "unique" { Just Unique }
| "unique0" { Just Unique0 }
| "priority" { Just Priority }
ForStep :: { [(LHS, AsgnOp, Expr)] }
: {- empty -} { [] }
......@@ -580,8 +670,19 @@ DeclsAndStmts :: { ([Decl], [Stmt]) }
| {- empty -} { ([], []) }
DeclOrStmt :: { ([Decl], [Stmt]) }
: DeclOrStmtTokens(";") { parseDTsAsDeclOrAsgn $1 }
| "parameter" ParamType DeclAsgns ";" { (map (uncurry $ Parameter $2) $3, []) }
| "localparam" ParamType DeclAsgns ";" { (map (uncurry $ Localparam $2) $3, []) }
| ParameterDecl(ParameterDeclKW, ";") { ($1, []) }
ParameterDecl(kw, delim) :: { [Decl] }
: kw DeclAsgns delim { map (uncurry $ $1 (Implicit Unspecified [])) $2 }
| kw ParamType DeclAsgns delim { map (uncurry $ $1 ($2 )) $3 }
| kw Identifier DeclAsgns delim { map (uncurry $ $1 (Alias $2 [])) $3 }
ParameterDeclKW :: { Type -> Identifier -> Expr -> Decl }
: "parameter" { Parameter }
| "localparam" { Localparam }
-- TODO: This does not allow for @identifier
ClockingEvent :: { Sense }
: "@" "(" Senses ")" { $3 }
TimingControl :: { Timing }
: DelayOrEventControl { $1 }
......@@ -615,10 +716,6 @@ DelayValue :: { Expr }
-- | time_literal
-- | 1step
Unique :: { Bool }
: "unique" { True }
| {- empty -} { False }
CaseKW :: { CaseKW }
: "case" { CaseN }
| "casex" { CaseX }
......@@ -716,6 +813,7 @@ PatternNamedItems :: { [(Identifier, Expr)] }
| PatternNamedItems "," PatternNamedItem { $1 ++ [$3] }
PatternNamedItem :: { (Identifier, Expr) }
: Identifier ":" Expr { ($1, $3) }
| "default" ":" Expr { (tokenString $1, $3) }
PatternUnnamedItems :: { [Expr] }
: Exprs { $1 }
......
src/Language/SystemVerilog/Parser/Tokens.hs
......@@ -225,6 +225,7 @@ data TokenName
| KW_type_option
| KW_union
| KW_unique
| KW_unique0
| KW_unsigned
| KW_use
| KW_uwire
......@@ -327,6 +328,8 @@ data TokenName
| Sym_gt_gt_eq
| Sym_bar_dash_gt
| Sym_bar_eq_gt
| Sym_pound_dash_pound
| Sym_pound_eq_pound
| Sym_brack_l_dash_gt
| Sym_at_at_paren_l
| Sym_paren_l_aster_paren_r
......
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