alias macromodule to module

a402a734 · Zachary Snow · 1a906840 · a402a734
Commit a402a734 authored Feb 01, 2020 by Zachary Snow
Show whitespace changes
Inline Side-by-side

Showing with 1 additions and 0 deletions

src/Language/SystemVerilog/Parser/Parse.y
+1 -0

No files found.
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -522,6 +522,7 @@ PartHeader :: { [Attr] -> Bool -> PartKW -> [ModuleItem] -> Description }
 ModuleKW :: { PartKW }
  : "module" { Module }
+  | "macromodule" { Module }
 InterfaceKW :: { PartKW }
  : "interface" { Interface }