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lvzhengyang
sv2v
Commits
a2b99fa9
Commit
a2b99fa9
authored
Jul 15, 2021
by
Zachary Snow
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module item statement traversals only visit the top level
parent
2eee536f
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11 changed files
with
25 additions
and
19 deletions
+25
-19
src/Convert/AsgnOp.hs
+1
-1
src/Convert/Assertion.hs
+2
-1
src/Convert/BlockDecl.hs
+1
-1
src/Convert/ForAsgn.hs
+1
-1
src/Convert/Foreach.hs
+1
-1
src/Convert/FuncRoutine.hs
+5
-2
src/Convert/Inside.hs
+1
-1
src/Convert/KWArgs.hs
+1
-1
src/Convert/NamedBlock.hs
+2
-1
src/Convert/Traverse.hs
+8
-8
src/Convert/Unique.hs
+2
-1
No files found.
src/Convert/AsgnOp.hs
View file @
a2b99fa9
...
...
@@ -14,7 +14,7 @@ import Language.SystemVerilog.AST
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
$
(
traverseStmts
convertStmt
(
traverseStmts
(
traverseNestedStmts
convertStmt
)
.
traverseGenItems
(
traverseNestedGenItems
convertGenItem
)
)
...
...
src/Convert/Assertion.hs
View file @
a2b99fa9
...
...
@@ -18,7 +18,8 @@ convertModuleItem (AssertionItem item) =
map
(
GenModuleItem
.
MIPackageItem
.
Decl
.
CommentDecl
)
$
"removed an assertion item"
:
(
lines
$
show
$
AssertionItem
item
)
convertModuleItem
other
=
traverseStmts
convertStmt
other
convertModuleItem
other
=
traverseStmts
(
traverseNestedStmts
convertStmt
)
other
convertStmt
::
Stmt
->
Stmt
convertStmt
(
Assertion
_
)
=
Null
...
...
src/Convert/BlockDecl.hs
View file @
a2b99fa9
...
...
@@ -16,7 +16,7 @@ import Language.SystemVerilog.AST
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
(
convertModuleItem
.
traverseStmts
convertStmt
)
(
convertModuleItem
.
traverseStmts
(
traverseNestedStmts
convertStmt
)
)
convertModuleItem
::
ModuleItem
->
ModuleItem
convertModuleItem
(
MIPackageItem
(
Function
ml
t
f
decls
stmts
))
=
...
...
src/Convert/ForAsgn.hs
View file @
a2b99fa9
...
...
@@ -17,7 +17,7 @@ import Language.SystemVerilog.AST
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
$
traverseStmts
convertStmt
traverseStmts
$
traverseNestedStmts
convertStmt
convertStmt
::
Stmt
->
Stmt
...
...
src/Convert/Foreach.hs
View file @
a2b99fa9
...
...
@@ -16,7 +16,7 @@ import Language.SystemVerilog.AST
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
$
traverseStmts
convertStmt
traverseStmts
$
traverseNestedStmts
convertStmt
convertStmt
::
Stmt
->
Stmt
convertStmt
(
Foreach
x
idxs
stmt
)
=
...
...
src/Convert/FuncRoutine.hs
View file @
a2b99fa9
...
...
@@ -23,8 +23,11 @@ convert = map $ traverseDescriptions convertDescription
convertDescription
::
Description
->
Description
convertDescription
(
description
@
Part
{})
=
traverseModuleItems
(
traverseStmts
$
convertStmt
functions
)
description
where
functions
=
execWriter
$
traverseModuleItems
traverseModuleItem
description
where
traverseModuleItem
=
traverseStmts
$
traverseNestedStmts
$
convertStmt
functions
functions
=
execWriter
$
collectModuleItemsM
collectFunctionsM
description
convertDescription
other
=
other
...
...
src/Convert/Inside.hs
View file @
a2b99fa9
...
...
@@ -28,7 +28,7 @@ convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
convertModuleItem
::
ModuleItem
->
ModuleItem
convertModuleItem
item
=
traverseExprs
(
traverseNestedExprs
convertExpr
)
$
traverseStmts
convertStmt
$
traverseStmts
(
traverseNestedStmts
convertStmt
)
$
item
convertExpr
::
Expr
->
Expr
...
...
src/Convert/KWArgs.hs
View file @
a2b99fa9
...
...
@@ -29,7 +29,7 @@ convertDescription description =
convertModuleItem
::
TFs
->
ModuleItem
->
ModuleItem
convertModuleItem
tfs
=
(
traverseExprs
$
traverseNestedExprs
$
convertExpr
tfs
)
.
(
traverseStmts
$
convertStmt
tfs
)
(
traverseStmts
$
traverseNestedStmts
$
convertStmt
tfs
)
collectTF
::
ModuleItem
->
Writer
TFs
()
collectTF
(
MIPackageItem
(
Function
_
_
f
decls
_
))
=
collectTFDecls
f
decls
...
...
src/Convert/NamedBlock.hs
View file @
a2b99fa9
...
...
@@ -23,7 +23,8 @@ convert asts =
-- we collect all the existing blocks in the first pass to make sure we
-- don't generate conflicting names on repeated passes of this conversion
evalState
(
runner
collectStmtM
asts
>>=
runner
traverseStmtM
)
Set
.
empty
where
runner
=
mapM
.
traverseDescriptionsM
.
traverseModuleItemsM
.
traverseStmtsM
where
runner
=
mapM
.
traverseDescriptionsM
.
traverseModuleItemsM
.
traverseStmtsM
.
traverseNestedStmtsM
collectStmtM
::
Stmt
->
State
Idents
Stmt
collectStmtM
(
Block
kw
x
decls
stmts
)
=
do
...
...
src/Convert/Traverse.hs
View file @
a2b99fa9
...
...
@@ -185,19 +185,18 @@ traverseStmtsM :: Monad m => MapperM m Stmt -> MapperM m ModuleItem
traverseStmtsM
mapper
=
moduleItemMapper
where
moduleItemMapper
(
AlwaysC
kw
stmt
)
=
fullM
apper
stmt
>>=
return
.
AlwaysC
kw
m
apper
stmt
>>=
return
.
AlwaysC
kw
moduleItemMapper
(
MIPackageItem
(
Function
lifetime
ret
name
decls
stmts
))
=
do
stmts'
<-
mapM
fullM
apper
stmts
stmts'
<-
mapM
m
apper
stmts
return
$
MIPackageItem
$
Function
lifetime
ret
name
decls
stmts'
moduleItemMapper
(
MIPackageItem
(
Task
lifetime
name
decls
stmts
))
=
do
stmts'
<-
mapM
fullM
apper
stmts
stmts'
<-
mapM
m
apper
stmts
return
$
MIPackageItem
$
Task
lifetime
name
decls
stmts'
moduleItemMapper
(
Initial
stmt
)
=
fullM
apper
stmt
>>=
return
.
Initial
m
apper
stmt
>>=
return
.
Initial
moduleItemMapper
(
Final
stmt
)
=
fullM
apper
stmt
>>=
return
.
Final
m
apper
stmt
>>=
return
.
Final
moduleItemMapper
other
=
return
$
other
fullMapper
=
traverseNestedStmtsM
mapper
traverseStmts
::
Mapper
Stmt
->
Mapper
ModuleItem
traverseStmts
=
unmonad
traverseStmtsM
...
...
@@ -719,7 +718,8 @@ collectStmtExprsM = collectify traverseStmtExprsM
traverseLHSsM
::
Monad
m
=>
MapperM
m
LHS
->
MapperM
m
ModuleItem
traverseLHSsM
mapper
=
traverseStmtsM
(
traverseStmtLHSsM
mapper
)
>=>
traverseModuleItemLHSsM
traverseStmtsM
(
traverseNestedStmtsM
$
traverseStmtLHSsM
mapper
)
>=>
traverseModuleItemLHSsM
where
traverseModuleItemLHSsM
(
Assign
delay
lhs
expr
)
=
do
lhs'
<-
mapper
lhs
...
...
@@ -1055,7 +1055,7 @@ traverseAsgnsM mapper = moduleItemMapper
return
$
Defparam
lhs'
expr'
miMapperA
other
=
return
other
miMapperB
=
traverseStmtsM
stmtMapper
miMapperB
=
traverseStmtsM
$
traverseNestedStmtsM
stmtMapper
stmtMapper
=
traverseStmtAsgnsM
mapper
traverseAsgns
::
Mapper
(
LHS
,
Expr
)
->
Mapper
ModuleItem
...
...
src/Convert/Unique.hs
View file @
a2b99fa9
...
...
@@ -15,7 +15,8 @@ import Language.SystemVerilog.AST
convert
::
[
AST
]
->
[
AST
]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
$
traverseStmts
convertStmt
map
$
traverseDescriptions
$
traverseModuleItems
$
traverseStmts
$
traverseNestedStmts
convertStmt
convertStmt
::
Stmt
->
Stmt
convertStmt
(
If
_
cc
s1
s2
)
=
...
...
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