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lvzhengyang
sv2v
Commits
a1cd6941
Commit
a1cd6941
authored
Oct 13, 2019
by
Zachary Snow
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apply patterns to substructures
parent
de581eca
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3 changed files
with
149 additions
and
0 deletions
+149
-0
src/Convert/Struct.hs
+6
-0
test/basic/pattern.sv
+29
-0
test/basic/pattern.v
+114
-0
No files found.
src/Convert/Struct.hs
View file @
a1cd6941
...
...
@@ -358,6 +358,9 @@ convertAsgn structs types (lhs, expr) =
-- look up by name
if
Map
.
member
fieldName
namedItemMap
then
namedItemMap
Map
.!
fieldName
-- recurse for substructures
else
if
isStruct
fieldType
then
Pattern
specialItems
-- look up by field type
else
if
Map
.
member
fieldTypeName
specialItemMap
then
specialItemMap
Map
.!
fieldTypeName
...
...
@@ -372,6 +375,9 @@ convertAsgn structs types (lhs, expr) =
fieldType
=
fieldTypeMap
Map
.!
fieldName
fieldTypeName
=
specialTag
:
(
show
$
fst
$
typeRanges
fieldType
)
isStruct
::
Type
->
Bool
isStruct
(
Struct
{})
=
True
isStruct
_
=
False
convertExpr
(
Struct
(
Packed
sg
)
fields
(
r
:
rs
))
subExpr
=
Repeat
(
rangeSize
r
)
[
subExpr'
]
...
...
test/basic/pattern.sv
View file @
a1cd6941
...
...
@@ -35,6 +35,35 @@ module test;
#
1
a
=
'
{
w
:
8
,
int
:
3
,
byte
:
2
,
default
:
0
};
end
typedef
struct
packed
{
int
x
;
struct_a
y
;
logic
z
;
}
struct_b
;
struct_b
b
;
initial
begin
#
100
;
$
monitor
(
"%2d: %b %b %b %b"
,
$
time
,
b
,
b
.
x
,
b
.
y
,
b
.
z
)
;
#
1
b
.
x
=
0
;
#
1
b
.
y
=
0
;
#
1
b
.
z
=
0
;
#
1
b
=
'
{
default
:
1
};
#
1
b
=
'
{
default
:
2
};
#
1
b
=
'
{
default
:
3
};
#
1
b
=
'
{
default
:
0
};
#
1
b
=
'
{
default
:
-
1
};
#
1
b
=
'
{
default
:
-
2
};
#
1
b
=
'
{
int
:
0
,
default
:
1
};
#
1
b
=
'
{
byte
:
0
,
default
:
1
};
#
1
b
=
'
{
logic
:
0
,
default
:
1
};
#
1
b
=
'
{
logic
:
1
,
int
:
2
,
byte
:
3
};
#
1
b
=
'
{
logic
:
1
,
int
:
2
,
byte
:
3
,
default
:
-
1
};
#
1
b
=
'
{
int
:
3
,
byte
:
2
,
default
:
0
};
end
endmodule
module
top
;
endmodule
test/basic/pattern.v
View file @
a1cd6941
...
...
@@ -113,6 +113,120 @@ module test;
a_z
=
0
;
end
end
reg
[
31
:
0
]
b_x
;
wire
[
72
:
0
]
b_y
;
reg
b_z
;
reg
[
105
:
0
]
b
;
assign
b_y
=
a
;
always
@*
b
=
{
b_x
,
b_y
,
b_z
};
initial
begin
#
100
;
a_w
=
'bx
;
a_x
=
'bx
;
a_y
=
'bx
;
a_z
=
'bx
;
$
monitor
(
"%2d: %b %b %b %b"
,
$
time
,
b
,
b_x
,
b_y
,
b_z
)
;
#
1
b_x
=
0
;
#
1
begin
a_w
=
0
;
a_x
=
0
;
a_y
=
0
;
a_z
=
0
;
end
#
1
b_z
=
0
;
#
1
begin
a_w
=
1
;
a_x
=
1
;
a_y
=
1
;
a_z
=
1
;
b_x
=
1
;
b_z
=
1
;
end
#
1
begin
a_w
=
2
;
a_x
=
2
;
a_y
=
2
;
a_z
=
2
;
b_x
=
2
;
b_z
=
2
;
end
#
1
begin
a_w
=
3
;
a_x
=
3
;
a_y
=
3
;
a_z
=
3
;
b_x
=
3
;
b_z
=
3
;
end
#
1
begin
a_w
=
0
;
a_x
=
0
;
a_y
=
0
;
a_z
=
0
;
b_x
=
0
;
b_z
=
0
;
end
#
1
begin
a_w
=
-
1
;
a_x
=
-
1
;
a_y
=
-
1
;
a_z
=
-
1
;
b_x
=
-
1
;
b_z
=
-
1
;
end
#
1
begin
a_w
=
-
2
;
a_x
=
-
2
;
a_y
=
-
2
;
a_z
=
-
2
;
b_x
=
-
2
;
b_z
=
-
2
;
end
#
1
begin
a_w
=
0
;
a_x
=
0
;
a_y
=
1
;
a_z
=
1
;
b_x
=
0
;
b_z
=
1
;
end
#
1
begin
a_w
=
1
;
a_x
=
1
;
a_y
=
0
;
a_z
=
1
;
b_x
=
1
;
b_z
=
1
;
end
#
1
begin
a_w
=
1
;
a_x
=
1
;
a_y
=
1
;
a_z
=
0
;
b_x
=
1
;
b_z
=
0
;
end
#
1
begin
a_w
=
2
;
a_x
=
2
;
a_y
=
3
;
a_z
=
1
;
b_x
=
2
;
b_z
=
1
;
end
#
1
;
#
1
begin
a_w
=
3
;
a_x
=
3
;
a_y
=
2
;
a_z
=
0
;
b_x
=
3
;
b_z
=
0
;
end
end
endmodule
...
...
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