Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
9eceb556
Commit
9eceb556
authored
May 02, 2022
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
defer elaboration of void functions
parent
b7a23276
Show whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
14 additions
and
5 deletions
+14
-5
src/Convert/EmptyArgs.hs
+4
-2
src/Convert/FuncRet.hs
+4
-1
src/Convert/FuncRoutine.hs
+1
-0
src/Convert/Traverse.hs
+1
-0
src/Language/SystemVerilog/AST/Type.hs
+3
-0
src/Language/SystemVerilog/Parser/Parse.y
+1
-2
No files found.
src/Convert/EmptyArgs.hs
View file @
9eceb556
...
...
@@ -30,14 +30,16 @@ convertDescription description@Part{} =
convertDescription
other
=
other
traverseFunctionsM
::
ModuleItem
->
Writer
Idents
ModuleItem
traverseFunctionsM
(
MIPackageItem
(
Function
ml
t
f
decls
stmts
))
=
do
traverseFunctionsM
item
@
(
MIPackageItem
(
Function
_
Void
_
_
_
))
=
return
item
traverseFunctionsM
(
MIPackageItem
(
Function
l
t
f
decls
stmts
))
=
do
decls'
<-
if
any
isInput
decls
then
return
decls
else
do
tell
$
Set
.
singleton
f
return
$
dummyDecl
:
decls
return
$
MIPackageItem
$
Function
m
l
t
f
decls'
stmts
return
$
MIPackageItem
$
Function
l
t
f
decls'
stmts
where
dummyType
=
IntegerVector
TReg
Unspecified
[]
dummyDecl
=
Variable
Input
dummyType
"_sv2v_unused"
[]
Nil
...
...
src/Convert/FuncRet.hs
View file @
9eceb556
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion which makes function `logic` and `reg` return types implicit
- Conversion which makes function `logic` and `reg` return types implicit and
- converts `void` functions to tasks
-
- Verilog-2005 restricts function return types to `integer`, `real`,
- `realtime`, `time`, and implicit signed/dimensioned types.
...
...
@@ -16,6 +17,8 @@ convert :: [AST] -> [AST]
convert
=
map
$
traverseDescriptions
$
traverseModuleItems
convertFunction
convertFunction
::
ModuleItem
->
ModuleItem
convertFunction
(
MIPackageItem
(
Function
ml
Void
f
decls
stmts
))
=
MIPackageItem
$
Task
ml
f
decls
stmts
convertFunction
(
MIPackageItem
(
Function
ml
t
f
decls
stmts
))
=
MIPackageItem
$
Function
ml
t'
f
decls
stmts
where
...
...
src/Convert/FuncRoutine.hs
View file @
9eceb556
...
...
@@ -32,6 +32,7 @@ convertDescription description@Part{} =
convertDescription
other
=
other
collectFunctionsM
::
ModuleItem
->
Writer
Idents
()
collectFunctionsM
(
MIPackageItem
(
Function
_
Void
_
_
_
))
=
return
()
collectFunctionsM
(
MIPackageItem
(
Function
_
_
f
_
_
))
=
tell
$
Set
.
singleton
f
collectFunctionsM
_
=
return
()
...
...
src/Convert/Traverse.hs
View file @
9eceb556
...
...
@@ -834,6 +834,7 @@ traverseSinglyNestedTypesM mapper = tm
tm
(
UnpackedType
t
r
)
=
do
t'
<-
mapper
t
return
$
UnpackedType
t'
r
tm
Void
=
return
Void
traverseSinglyNestedTypes
::
Mapper
Type
->
Mapper
Type
traverseSinglyNestedTypes
=
unmonad
traverseSinglyNestedTypesM
...
...
src/Language/SystemVerilog/AST/Type.hs
View file @
9eceb556
...
...
@@ -52,6 +52,7 @@ data Type
|
TypeOf
Expr
|
TypedefRef
Expr
|
UnpackedType
Type
[
Range
]
-- used internally
|
Void
deriving
Eq
instance
Show
Type
where
...
...
@@ -74,6 +75,7 @@ instance Show Type where
show
(
TypeOf
expr
)
=
printf
"type(%s)"
(
show
expr
)
show
(
UnpackedType
t
rs
)
=
printf
"UnpackedType(%s, %s)"
(
show
t
)
(
showRanges
rs
)
show
(
TypedefRef
e
)
=
show
e
show
Void
=
"void"
showFields
::
[
Field
]
->
String
showFields
items
=
itemsStr
...
...
@@ -102,6 +104,7 @@ typeRanges typ =
NonInteger
kw
->
(
nullRange
$
NonInteger
kw
,
[]
)
TypeOf
expr
->
(
nullRange
$
TypeOf
expr
,
[]
)
TypedefRef
expr
->
(
nullRange
$
TypedefRef
expr
,
[]
)
Void
->
(
nullRange
Void
,
[]
)
nullRange
::
Type
->
([
Range
]
->
Type
)
nullRange
t
[]
=
t
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
9eceb556
...
...
@@ -924,7 +924,6 @@ ImportOrExport :: { [PackageItem] }
|
"export"
"*"
"::"
"*"
";"
{
[
Export
""
""
]
}
TaskOrFunction
::
{
PackageItem
}
:
"function"
Lifetime
FuncRetAndName
TFItems
DeclsAndStmts
endfunction
StrTag
{
%
checkTag
(
snd
$
3
)
$
7
$
Function
$
2
(
fst
$
3
)
(
snd
$
3
)
(
map
makeInput
$
4
++
fst
$
5
)
(
snd
$
5
)
}
|
"function"
Lifetime
"void"
Identifier
TFItems
DeclsAndStmts
endfunction
StrTag
{
%
checkTag
$
4
$
8
$
Task
$
2
$
4
(
$
5
++
fst
$
6
)
(
snd
$
6
)
}
|
"task"
Lifetime
Identifier
TFItems
DeclsAndStmts
endtask
StrTag
{
%
checkTag
$
3
$
7
$
Task
$
2
$
3
(
$
4
++
fst
$
5
)
(
snd
$
5
)
}
Typedef
::
{
Decl
}
:
"typedef"
Type
Identifier
";"
{
ParamType
Localparam
$
3
$
2
}
...
...
@@ -965,7 +964,6 @@ OptDPIImportProperty :: { DPIImportProperty }
DPITFProto
::
{
(
Type
,
Identifier
,
[
Decl
])
}
:
"function"
FuncRetAndName
TFItems
{
(
fst
$
2
,
snd
$
2
,
$
3
)
}
|
"function"
"void"
Identifier
TFItems
{
(
UnknownType
,
$
3
,
$
4
)
}
|
"task"
Identifier
TFItems
{
(
UnknownType
,
$
2
,
$
3
)
}
Directive
::
{
String
}
...
...
@@ -995,6 +993,7 @@ FuncRetAndName :: { (Type, Identifier) }
|
Signing
Identifier
{
(
Implicit
$
1
[]
,
$
2
)
}
|
DimensionsNonEmpty
Identifier
{
(
Implicit
Unspecified
$
1
,
$
2
)
}
|
Signing
DimensionsNonEmpty
Identifier
{
(
Implicit
$
1
$
2
,
$
3
)
}
|
"void"
Identifier
{
(
Void
,
$
2
)
}
AlwaysKW
::
{
AlwaysKW
}
:
"always"
{
Always
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment