use iverilog 11 in Linux CI

.github/workflows/main.yaml

@@ -47,7 +47,27 @@ jobs:
         run: brew install shunit2 icarus-verilog
       - name: Install Dependencies (Linux)
         if: runner.os == 'Linux'
-        run: sudo apt-get install -y shunit2 iverilog
+        run: sudo apt-get install -y shunit2 flex bison autoconf gperf
+      - name: Cache iverilog (Linux)
+        uses: actions/cache@v2
+        if: runner.os == 'Linux'
+        with:
+          path: ~/.local
+          key: ${{ runner.OS }}-iverilog-11_0
+          restore-keys: ${{ runner.OS }}-iverilog-11_0
+      - name: Install iverilog (Linux)
+        if: runner.os == 'Linux'
+        run: |
+          if [ ! -e "$HOME/.local/bin/iverilog" ]; then
+            curl -L https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz > iverilog.tar.gz
+            tar -xzf iverilog.tar.gz
+            cd iverilog-11_0
+            autoconf
+            ./configure --prefix=$HOME/.local
+            make
+            make install
+            cd ..
+          fi
       - name: Download Artifact
         uses: actions/download-artifact@v1
         with:

test/basic/local_cast.sv

@@ -15,11 +15,10 @@ module top;
                 end
             end
         end
-        // TODO: This is not yet supported by iverilog
-        // localparam P = 2;
-        // for (genvar i = 0; i < int'(P); i = i + 1) begin : g
-        //     wire a = i;
-        // end
-        // initial $display("%b %b", g[0].a, g[1].a);
+        localparam P = 2;
+        for (genvar i = 0; i < byte'(P); i = i + 1) begin : g
+            wire a = i;
+        end
+        initial $display("%b %b", g[0].a, g[1].a);
     endgenerate
 endmodule

test/basic/local_cast.v

@@ -20,11 +20,10 @@ module top;
                 cast_i = inp;
             endfunction
         end
-        // TODO: This is not yet supported by iverilog
-        // localparam P = 2;
-        // for (i = 0; i < P; i = i + 1) begin : g
-        //     wire a = i;
-        // end
-        // initial $display("%b %b", g[0].a, g[1].a);
+        localparam P = 2;
+        for (i = 0; i < P; i = i + 1) begin : g
+            wire a = i;
+        end
+        initial $display("%b %b", g[0].a, g[1].a);
     endgenerate
 endmodule

test/basic/typeof_op.sv

 `define TEST(expr) \
-    $display(`"expr = %b; $bits(expr) = %0d`", (expr), $bits(expr));
+    $display("%s = %b; $bits(%s) = %0d", `"expr`", expr, `"expr`", $bits(expr));
 
 module top;
     initial begin
@@ -37,19 +37,18 @@ module top;
         `TEST(4'b1011 > 5'b01110)
         `TEST(4'b1011 >= 5'b01110)
 
-        // TODO: iverilog incorrectly handles width of these
-        // `TEST(4'b1011 * 5'b01110)
-        // `TEST(4'b1011 / 5'b01110)
-        // `TEST(4'b1011 % 5'b01110)
-        // `TEST(4'b1011 + 5'b01110)
-        // `TEST(4'b1011 - 5'b01110)
-        // `TEST(4'b1011 ** 5'b01110)
+        `TEST(4'b1011 * 5'b01110)
+        `TEST(4'b1011 / 5'b01110)
+        `TEST(4'b1011 % 5'b01110)
+        `TEST(4'b1011 + 5'b01110)
+        `TEST(4'b1011 - 5'b01110)
+        `TEST(4'b1011 ** 5'b01110)
+        `TEST(4'b1011 <-> 5'b01110)
+        `TEST(4'b1011 ==? 5'b01110)
+        `TEST(4'b1011 !=? 5'b01110)
 
         // TODO: not yet supported by iverilog
         // `TEST(4'b1011 -> 5'b01110)
-        // `TEST(4'b1011 <-> 5'b01110)
-        // `TEST(4'b1011 ==? 5'b01110)
-        // `TEST(4'b1011 !=? 5'b01110)
 
     end
 endmodule