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lvzhengyang
sv2v
Commits
96cfe18c
Commit
96cfe18c
authored
Feb 07, 2022
by
Zachary Snow
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pass through support for functions with output ports
parent
eb42042c
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14 additions
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1 deletions
+14
-1
CHANGELOG.md
+1
-0
src/Language/SystemVerilog/Parser/Parse.y
+2
-1
test/nosim/func_output.sv
+11
-0
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CHANGELOG.md
View file @
96cfe18c
...
...
@@ -6,6 +6,7 @@
`'1`
,
`'x`
) via
`--exclude UnbasedUniszed`
*
Added support for enumerated type ranges (e.g.,
`enum { X[3:5] }`
)
*
Added support for passing through DPI imports and exports
*
Added support for passing through functions with output ports
### Other Enhancements
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
96cfe18c
...
...
@@ -1571,9 +1571,10 @@ combineDeclsAndStmts (a1, b1) (a2, b2) =
makeInput
::
Decl
->
Decl
makeInput
(
Variable
Local
t
x
a
e
)
=
Variable
Input
t
x
a
e
makeInput
(
Variable
Input
t
x
a
e
)
=
Variable
Input
t
x
a
e
makeInput
(
Variable
Output
t
x
a
e
)
=
Variable
Output
t
x
a
e
makeInput
(
CommentDecl
c
)
=
CommentDecl
c
makeInput
other
=
error
$
"unexpected non-var or non-
input
decl: "
++
(
show
other
)
error
$
"unexpected non-var or non-
port function
decl: "
++
(
show
other
)
checkTag
::
String
->
String
->
a
->
ParseState
a
checkTag
_
""
x
=
return
x
...
...
test/nosim/func_output.sv
0 → 100644
View file @
96cfe18c
module
top
;
function
automatic
integer
f
;
input
integer
x
;
output
integer
y
;
f
=
x
*
3
;
y
=
x
*
5
;
endfunction
integer
x
,
y
;
initial
x
=
f
(
-
1
,
y
)
;
initial
$
display
(
x
,
y
)
;
endmodule
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