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lvzhengyang
sv2v
Commits
8a67a911
Commit
8a67a911
authored
Aug 08, 2019
by
Zachary Snow
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added language support for (untagged) unions
parent
ae239f16
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Showing
5 changed files
with
20 additions
and
5 deletions
+20
-5
src/Convert/Traverse.hs
+4
-0
src/Convert/Typedef.hs
+6
-4
src/Language/SystemVerilog/AST/Type.hs
+7
-1
src/Language/SystemVerilog/Parser/Lex.x
+1
-0
src/Language/SystemVerilog/Parser/Parse.y
+2
-0
No files found.
src/Convert/Traverse.hs
View file @
8a67a911
...
...
@@ -785,6 +785,10 @@ traverseTypesM mapper item =
types
<-
mapM
fullMapper
$
map
fst
fields
let
idents
=
map
snd
fields
return
$
Struct
p
(
zip
types
idents
)
r
tm
(
Union
p
fields
r
)
=
do
types
<-
mapM
fullMapper
$
map
fst
fields
let
idents
=
map
snd
fields
return
$
Union
p
(
zip
types
idents
)
r
exprMapper
(
Cast
(
Left
t
)
e
)
=
fullMapper
t
>>=
\
t'
->
return
$
Cast
(
Left
t'
)
e
exprMapper
(
Bits
(
Left
t
))
=
...
...
src/Convert/Typedef.hs
View file @
8a67a911
...
...
@@ -54,6 +54,9 @@ convertDescription globalTypes description =
else
Bits
$
Right
$
Ident
x
convertExpr
other
=
other
resolveItem
::
Types
->
(
Type
,
Identifier
)
->
(
Type
,
Identifier
)
resolveItem
types
(
t
,
x
)
=
(
resolveType
types
t
,
x
)
resolveType
::
Types
->
Type
->
Type
resolveType
_
(
Net
kw
rs
)
=
Net
kw
rs
resolveType
_
(
Implicit
sg
rs
)
=
Implicit
sg
rs
...
...
@@ -64,10 +67,8 @@ resolveType _ (InterfaceT x my rs) = InterfaceT x my rs
resolveType
_
(
Enum
Nothing
vals
rs
)
=
Enum
Nothing
vals
rs
resolveType
_
(
Alias
(
Just
ps
)
st
rs
)
=
Alias
(
Just
ps
)
st
rs
resolveType
types
(
Enum
(
Just
t
)
vals
rs
)
=
Enum
(
Just
$
resolveType
types
t
)
vals
rs
resolveType
types
(
Struct
p
items
rs
)
=
Struct
p
items'
rs
where
items'
=
map
resolveItem
items
resolveItem
(
t
,
x
)
=
(
resolveType
types
t
,
x
)
resolveType
types
(
Struct
p
items
rs
)
=
Struct
p
(
map
(
resolveItem
types
)
items
)
rs
resolveType
types
(
Union
p
items
rs
)
=
Union
p
(
map
(
resolveItem
types
)
items
)
rs
resolveType
types
(
Alias
Nothing
st
rs1
)
=
if
Map
.
notMember
st
types
then
InterfaceT
st
Nothing
rs1
...
...
@@ -77,6 +78,7 @@ resolveType types (Alias Nothing st rs1) =
(
IntegerVector
kw
sg
rs2
)
->
IntegerVector
kw
sg
$
rs1
++
rs2
(
Enum
t
v
rs2
)
->
Enum
t
v
$
rs1
++
rs2
(
Struct
p
l
rs2
)
->
Struct
p
l
$
rs1
++
rs2
(
Union
p
l
rs2
)
->
Union
p
l
$
rs1
++
rs2
(
InterfaceT
x
my
rs2
)
->
InterfaceT
x
my
$
rs1
++
rs2
(
IntegerAtom
kw
_
)
->
error
$
"resolveType encountered packed `"
++
(
show
kw
)
++
"` on "
++
st
(
NonInteger
kw
)
->
error
$
"resolveType encountered packed `"
++
(
show
kw
)
++
"` on "
++
st
...
...
src/Language/SystemVerilog/AST/Type.hs
View file @
8a67a911
...
...
@@ -37,6 +37,7 @@ data Type
|
Alias
(
Maybe
Identifier
)
Identifier
[
Range
]
|
Enum
(
Maybe
Type
)
[
Item
]
[
Range
]
|
Struct
Packing
[
Field
]
[
Range
]
|
Union
Packing
[
Field
]
[
Range
]
|
InterfaceT
Identifier
(
Maybe
Identifier
)
[
Range
]
deriving
(
Eq
,
Ord
)
...
...
@@ -54,7 +55,11 @@ instance Show Type where
tStr
=
maybe
""
showPad
mt
showVal
::
(
Identifier
,
Maybe
Expr
)
->
String
showVal
(
x
,
e
)
=
x
++
(
showAssignment
e
)
show
(
Struct
p
items
r
)
=
printf
"struct %s{
\n
%s
\n
}%s"
(
showPad
p
)
itemsStr
(
showRanges
r
)
show
(
Struct
p
items
r
)
=
printf
"struct %s{
\n
%s
\n
}%s"
(
showPad
p
)
(
showFields
items
)
(
showRanges
r
)
show
(
Union
p
items
r
)
=
printf
"union %s{
\n
%s
\n
}%s"
(
showPad
p
)
(
showFields
items
)
(
showRanges
r
)
showFields
::
[
Field
]
->
String
showFields
items
=
itemsStr
where
itemsStr
=
indent
$
unlines'
$
map
showItem
items
showItem
(
t
,
x
)
=
printf
"%s %s;"
(
show
t
)
x
...
...
@@ -82,6 +87,7 @@ typeRanges (IntegerAtom kw sg ) = (\[] -> IntegerAtom kw sg, [])
typeRanges
(
NonInteger
kw
)
=
(
\
[]
->
NonInteger
kw
,
[]
)
typeRanges
(
Enum
t
v
r
)
=
(
Enum
t
v
,
r
)
typeRanges
(
Struct
p
l
r
)
=
(
Struct
p
l
,
r
)
typeRanges
(
Union
p
l
r
)
=
(
Union
p
l
,
r
)
typeRanges
(
InterfaceT
x
my
r
)
=
(
InterfaceT
x
my
,
r
)
data
Signing
...
...
src/Language/SystemVerilog/Parser/Lex.x
View file @
8a67a911
...
...
@@ -197,6 +197,7 @@ tokens :-
"trior" { tok KW_trior }
"trireg" { tok KW_trireg }
"typedef" { tok KW_typedef }
"union" { tok KW_union }
"unique" { tok KW_unique }
"unique0" { tok KW_unique0 }
"unsigned" { tok KW_unsigned }
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
8a67a911
...
...
@@ -115,6 +115,7 @@ import Language.SystemVerilog.Parser.Tokens
"trior" { Token KW_trior _ _ }
"trireg" { Token KW_trireg _ _ }
"typedef" { Token KW_typedef _ _ }
"union" { Token KW_union _ _ }
"unique" { Token KW_unique _ _ }
"unique0" { Token KW_unique0 _ _ }
"unsigned" { Token KW_unsigned _ _ }
...
...
@@ -277,6 +278,7 @@ PartialType :: { Signing -> [Range] -> Type }
| NonIntegerType { \Unspecified -> \[] -> NonInteger $1 }
| "enum" EnumBaseType "{" EnumItems "}" { \Unspecified -> Enum $2 $4 }
| "struct" Packing "{" StructItems "}" { \Unspecified -> Struct $2 $4 }
| "union" Packing "{" StructItems "}" { \Unspecified -> Union $2 $4 }
CastingType :: { Type }
: IntegerVectorType { IntegerVector $1 Unspecified [] }
| IntegerAtomType { IntegerAtom $1 Unspecified }
...
...
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