simple conversion for unbased unsized literals

src/Convert.hs

@@ -20,6 +20,7 @@ import qualified Convert.Return
 import qualified Convert.StarPort
 import qualified Convert.Struct
 import qualified Convert.Typedef
+import qualified Convert.UnbasedUnsized
 import qualified Convert.Unique
 
 type Phase = AST -> AST
@@ -35,6 +36,7 @@ phases excludes =
     , Convert.Struct.convert
     , Convert.Return.convert
     , Convert.Typedef.convert
+    , Convert.UnbasedUnsized.convert
     , Convert.Unique.convert
     ]
     where

src/Convert/UnbasedUnsized.hs

+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for unbased, unsized literals ('0, '1, 'z, 'x)
+ -
+ - Maintaining the unsized-ness of the literals is critical, but those digits
+ - are all equivalent regardless of base. We simply convert them to all use a
+ - binary base for compatability with Verilog-2005.
+ -}
+
+module Convert.UnbasedUnsized (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: AST -> AST
+convert =
+    traverseDescriptions $ traverseModuleItems $
+    traverseExprs $ traverseNestedExprs convertExpr
+
+digits :: [Char]
+digits = ['0', '1', 'x', 'z', 'X', 'Z']
+
+convertExpr :: Expr -> Expr
+convertExpr (Number ['\'', ch]) =
+    if elem ch digits
+        then Number ("'b" ++ [ch])
+        else error $ "unexpected unbased-unsized digit: " ++ [ch]
+convertExpr other = other

sv2v.cabal

@@ -53,6 +53,7 @@ executable sv2v
     Convert.Struct
     Convert.Typedef
     Convert.Traverse
+    Convert.UnbasedUnsized
     Convert.Unique
     -- sv2v CLI modules
     Job