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lvzhengyang
sv2v
Commits
76663c78
Commit
76663c78
authored
Sep 25, 2019
by
Zachary Snow
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fix typename decl asgn lookahead (resolves #49)
parent
c7f51209
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3 changed files
with
27 additions
and
4 deletions
+27
-4
src/Language/SystemVerilog/Parser/ParseDecl.hs
+14
-4
test/basic/port_typename.sv
+7
-0
test/basic/port_typename.v
+6
-0
No files found.
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
76663c78
...
...
@@ -360,12 +360,22 @@ takeLifetime rest = (Nothing, rest)
takeType
::
[
DeclToken
]
->
([
Range
]
->
Type
,
[
DeclToken
])
takeType
(
DTIdent
a
:
DTDot
b
:
rest
)
=
(
InterfaceT
a
(
Just
b
),
rest
)
takeType
(
DTType
tf
:
DTSigning
sg
:
rest
)
=
(
tf
sg
,
rest
)
takeType
(
DTType
tf
:
rest
)
=
(
tf
Unspecified
,
rest
)
takeType
(
DTType
tf
:
rest
)
=
(
tf
Unspecified
,
rest
)
takeType
(
DTSigning
sg
:
rest
)
=
(
Implicit
sg
,
rest
)
takeType
(
DTIdent
tn
:
DTComma
:
rest
)
=
(
Implicit
Unspecified
,
DTIdent
tn
:
DTComma
:
rest
)
takeType
(
DTIdent
tn
:
[ ]
)
=
(
Implicit
Unspecified
,
DTIdent
tn
:
[ ]
)
takeType
(
DTIdent
tn
:
rest
)
=
(
Alias
(
Nothing
)
tn
,
rest
)
takeType
(
DTPSIdent
ps
tn
:
rest
)
=
(
Alias
(
Just
ps
)
tn
,
rest
)
takeType
(
DTIdent
tn
:
rest
)
=
if
couldBeTypename
then
(
Alias
(
Nothing
)
tn
,
rest
)
else
(
Implicit
Unspecified
,
DTIdent
tn
:
rest
)
where
couldBeTypename
=
case
(
findIndex
isIdent
rest
,
elemIndex
DTComma
rest
)
of
-- no identifiers left => no decl asgns
(
Nothing
,
_
)
->
False
-- an identifier is left, and no more commas
(
_
,
Nothing
)
->
True
-- if comma is first, then this ident is a declaration
(
Just
a
,
Just
b
)
->
a
<
b
takeType
rest
=
(
Implicit
Unspecified
,
rest
)
takeRanges
::
[
DeclToken
]
->
([
Range
],
[
DeclToken
])
...
...
test/basic/port_typename.sv
0 → 100644
View file @
76663c78
typedef
wire
b_t
;
module
top
(
input
a
[
1
:
0
]
,
input
b_t
b
)
;
initial
$
display
(
"%d %d %1d %1d"
,
a
,
b
,
$
bits
(
a
)
,
$
bits
(
b
))
;
endmodule
test/basic/port_typename.v
0 → 100644
View file @
76663c78
module
top
(
input
[
1
:
0
]
a
,
input
wire
b
)
;
initial
$
display
(
"%d %d %1d %1d"
,
a
,
b
,
$
bits
(
a
)
,
$
bits
(
b
))
;
endmodule
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