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lvzhengyang
sv2v
Commits
6ddf7823
Commit
6ddf7823
authored
Sep 11, 2019
by
Zachary Snow
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drop timeunit and timescale (closes #31)
parent
295ac649
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5 changed files
with
42 additions
and
1 deletions
+42
-1
src/Language/SystemVerilog/Parser/Lex.x
+8
-0
src/Language/SystemVerilog/Parser/Parse.y
+9
-0
src/Language/SystemVerilog/Parser/Tokens.hs
+1
-1
test/basic/time.sv
+21
-0
test/basic/time.v
+3
-0
No files found.
src/Language/SystemVerilog/Parser/Lex.x
View file @
6ddf7823
...
...
@@ -85,6 +85,13 @@ $decimalDigit = [0-9]
@string = \" (\\\"|[^\"\r\n])* \"
-- Times
@timeUnit = s | ms | us | ns | ps | fs
@time
= @unsignedNumber @timeUnit
| @fixedPointNumber @timeUnit
-- Identifiers
@escapedIdentifier = "\" ($printable # $white)+ $white
...
...
@@ -364,6 +371,7 @@ tokens :-
@number { tok Lit_number }
@string { tok Lit_string }
@time { tok Lit_time }
"(" { tok Sym_paren_l }
")" { tok Sym_paren_r }
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
6ddf7823
...
...
@@ -281,6 +281,7 @@ escapedIdentifier { Token Id_escaped _ _ }
systemIdentifier { Token Id_system _ _ }
number { Token Lit_number _ _ }
string { Token Lit_string _ _ }
time { Token Lit_time _ _ }
"(" { Token Sym_paren_l _ _ }
")" { Token Sym_paren_r _ _ }
...
...
@@ -738,10 +739,15 @@ NonDeclPackageItem :: { [PackageItem] }
| "export" PackageImportItems ";" { map (Export . Just) $2 }
| "export" "*" "::" "*" ";" { [Export Nothing] } -- "Nothing" being no restrictions
| ForwardTypedef ";" { $1 }
| TimeunitsDeclaration { $1 }
ForwardTypedef :: { [PackageItem] }
: "typedef" "enum" Identifier { [] }
| "typedef" "struct" Identifier { [] }
| "typedef" "union" Identifier { [] }
TimeunitsDeclaration :: { [PackageItem] }
: "timeunit" Time ";" { [] }
| "timeunit" Time "/" Time ";" { [] }
| "timeprecision" Time ";" { [] }
PackageImportItems :: { [(Identifier, Maybe Identifier)] }
: PackageImportItem { [$1] }
...
...
@@ -970,6 +976,9 @@ Number :: { String }
String :: { String }
: string { tail $ init $ tokenString $1 }
Time :: { String }
: time { tokenString $1 }
CallArgs :: { Args }
: {- empty -} { Args [ ] [] }
| NamedCallArgsFollow { Args [ ] $1 }
...
...
src/Language/SystemVerilog/Parser/Tokens.hs
View file @
6ddf7823
...
...
@@ -281,9 +281,9 @@ data TokenName
|
Id_simple
|
Id_escaped
|
Id_system
|
Lit_number_unsigned
|
Lit_number
|
Lit_string
|
Lit_time
|
Sym_paren_l
|
Sym_paren_r
|
Sym_brack_l
...
...
test/basic/time.sv
0 → 100644
View file @
6ddf7823
`timescale
1
ns
/
10
ps
timeunit
100
ps
;
timeprecision
1
ps
;
module
top_1
;
`timescale
1
ns
/
10
ps
timeunit
1
ps
;
timeprecision
1
ps
;
endmodule
module
top_2
;
timeunit
100
ps
/
10
fs
;
endmodule
module
top_3
;
timeunit
10.0
ps
/
10
fs
;
endmodule
module
top_4
;
timeunit
100
ps
;
timeprecision
10
fs
;
endmodule
module
top
;
initial
$
display
(
"Hello!"
)
;
endmodule
test/basic/time.v
0 → 100644
View file @
6ddf7823
module
top
;
initial
$
display
(
"Hello!"
)
;
endmodule
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