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lvzhengyang
sv2v
Commits
698e3b0b
Commit
698e3b0b
authored
Jul 27, 2020
by
Zachary Snow
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fix unbased unsized binding conversion for instances with type parameters
parent
50d6faa9
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2 changed files
with
12 additions
and
5 deletions
+12
-5
src/Convert/UnbasedUnsized.hs
+7
-1
test/basic/unbased_unsized.sv
+5
-4
No files found.
src/Convert/UnbasedUnsized.hs
View file @
698e3b0b
...
@@ -47,13 +47,19 @@ collectPartsM _ = return ()
...
@@ -47,13 +47,19 @@ collectPartsM _ = return ()
convertModuleItem
::
Parts
->
ModuleItem
->
ModuleItem
convertModuleItem
::
Parts
->
ModuleItem
->
ModuleItem
convertModuleItem
parts
(
Instance
moduleName
params
instanceName
[]
bindings
)
=
convertModuleItem
parts
(
Instance
moduleName
params
instanceName
[]
bindings
)
=
convertModuleItem'
$
Instance
moduleName
params
instanceName
[]
bindings'
if
Map
.
member
moduleName
parts
&&
not
(
any
isTypeParam
moduleItems
)
then
convertModuleItem'
$
Instance
moduleName
params
instanceName
[]
bindings'
else
Instance
moduleName
params
instanceName
[]
bindings
where
where
bindings'
=
zipWith
convertBinding
bindings
[
0
..
]
bindings'
=
zipWith
convertBinding
bindings
[
0
..
]
(
portNames
,
moduleItems
)
=
(
portNames
,
moduleItems
)
=
case
Map
.
lookup
moduleName
parts
of
case
Map
.
lookup
moduleName
parts
of
Nothing
->
error
$
"could not find module: "
++
moduleName
Nothing
->
error
$
"could not find module: "
++
moduleName
Just
partInfo
->
partInfo
Just
partInfo
->
partInfo
isTypeParam
::
ModuleItem
->
Bool
isTypeParam
(
MIPackageItem
(
Decl
ParamType
{}))
=
True
isTypeParam
_
=
False
tag
=
Ident
"~~uub~~"
tag
=
Ident
"~~uub~~"
convertBinding
::
PortBinding
->
Int
->
PortBinding
convertBinding
::
PortBinding
->
Int
->
PortBinding
convertBinding
(
portName
,
expr
)
idx
=
convertBinding
(
portName
,
expr
)
idx
=
...
...
test/basic/unbased_unsized.sv
View file @
698e3b0b
...
@@ -130,9 +130,10 @@ endmodule
...
@@ -130,9 +130,10 @@ endmodule
module
M
(
a
,
b
,
c
,
d
)
;
module
M
(
a
,
b
,
c
,
d
)
;
parameter
W
=
1
;
parameter
W
=
1
;
input
logic
[
W
+
0
:
1
]
a
;
parameter
type
T
=
logic
;
input
logic
[
W
+
1
:
1
]
b
;
input
T
[
W
+
0
:
1
]
a
;
input
logic
[
W
+
2
:
1
]
c
;
input
T
[
W
+
1
:
1
]
b
;
input
logic
[
W
+
3
:
1
]
d
;
input
T
[
W
+
2
:
1
]
c
;
input
T
[
W
+
3
:
1
]
d
;
initial
$
display
(
"M W=%0d %b %b %b %b"
,
W
,
a
,
b
,
c
,
d
)
;
initial
$
display
(
"M W=%0d %b %b %b %b"
,
W
,
a
,
b
,
c
,
d
)
;
endmodule
endmodule
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