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lvzhengyang
sv2v
Commits
646cb21b
Commit
646cb21b
authored
May 07, 2023
by
Zachary Snow
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646cb21b
...
@@ -12,11 +12,11 @@ conversion already exist, they generally either rely on commercial tools, or are
...
@@ -12,11 +12,11 @@ conversion already exist, they generally either rely on commercial tools, or are
limited in scope.
limited in scope.
This project was originally developed to target
[
Yosys
]
, and so allows for
This project was originally developed to target
[
Yosys
]
, and so allows for
disabling the conversion of (passing through) those
[
SystemVerilog features
disabling the conversion of (passing through) those
[
SystemVerilog features
that
which
Yosys supports].
Yosys supports].
[
Yosys
]:
http
://www.clifford.a
t/yosys/
[
Yosys
]:
http
s://yosyshq.ne
t/yosys/
[
SystemVerilog features
which
Yosys supports
]:
https://github.com/YosysHQ/yosys#supported-features-from-systemverilog
[
SystemVerilog features
that
Yosys supports
]:
https://github.com/YosysHQ/yosys#supported-features-from-systemverilog
The idea for this project was shared with me while I was an undergraduate at
The idea for this project was shared with me while I was an undergraduate at
Carnegie Mellon University as part of a joint Computer Science and Electrical
Carnegie Mellon University as part of a joint Computer Science and Electrical
...
@@ -36,7 +36,8 @@ All of sv2v's dependencies are free and open-source.
...
@@ -36,7 +36,8 @@ All of sv2v's dependencies are free and open-source.
*
[
Haskell Stack
](
https://www.haskellstack.org/
)
- Haskell build system
*
[
Haskell Stack
](
https://www.haskellstack.org/
)
- Haskell build system
*
Haskell dependencies are managed in
`sv2v.cabal`
*
Haskell dependencies are managed in
`sv2v.cabal`
*
Test Dependencies
*
Test Dependencies
*
[
Icarus Verilog
](
http://iverilog.icarus.com
)
- for Verilog simulation
*
[
Icarus Verilog
](
https://steveicarus.github.io/iverilog/
)
- for Verilog
simulation
*
[
shUnit2
](
https://github.com/kward/shunit2
)
- test framework
*
[
shUnit2
](
https://github.com/kward/shunit2
)
- test framework
*
Python (any version) - for generating certain test cases
*
Python (any version) - for generating certain test cases
...
@@ -72,16 +73,18 @@ running `stack install`, or copy over the executable manually.
...
@@ -72,16 +73,18 @@ running `stack install`, or copy over the executable manually.
## Usage
## Usage
sv2v takes in a list of files and prints the converted Verilog to
`stdout`
.
sv2v takes in a list of files and prints the converted Verilog to
`stdout`
by
Using
`--write=adjacent`
will create a converted
`.v`
for every
`.sv`
input file
default. Users should typically pass all of their SystemVerilog source files to
rather than printing to
`stdout`
.
`--write`
/
`-w`
can also be used to specify a
sv2v at once so it can properly resolve packages, interfaces, type parameters,
path to a
`.v`
output file.
etc., across files. Using
`--write=adjacent`
will create a converted
`.v`
for
every
`.sv`
input file rather than printing to
`stdout`
.
`--write`
/
`-w`
can also
be used to specify a path to a
`.v`
output file.
Users may specify
`include`
search paths, define macros during preprocessing,
Users may specify
`include`
search paths, define macros during preprocessing,
and exclude some of the conversions. Specifying
`-`
as an input file will read
and exclude some of the conversions. Specifying
`-`
as an input file will read
from
`stdin`
.
from
`stdin`
.
Below is the current usage printout.
This interface is subject to change.
Below is the current usage printout.
```
```
sv2v [OPTIONS] [FILES]
sv2v [OPTIONS] [FILES]
...
@@ -119,7 +122,7 @@ usages of parameterized classes, and the `bind` keyword. Assertions are also
...
@@ -119,7 +122,7 @@ usages of parameterized classes, and the `bind` keyword. Assertions are also
supported, but are simply dropped during conversion.
supported, but are simply dropped during conversion.
If you find a bug or have a feature request, please
[
create an issue
]
.
If you find a bug or have a feature request, please
[
create an issue
]
.
Preference will be given to issues
which
include examples or test cases.
Preference will be given to issues
that
include examples or test cases.
[
create an issue
]:
https://github.com/zachjs/sv2v/issues/new
[
create an issue
]:
https://github.com/zachjs/sv2v/issues/new
...
@@ -144,7 +147,7 @@ There is also a [SystemVerilog compliance suite] being created to test
...
@@ -144,7 +147,7 @@ There is also a [SystemVerilog compliance suite] being created to test
open-source tools' SystemVerilog support. Although not every test in the suite
open-source tools' SystemVerilog support. Although not every test in the suite
is applicable, it has been a valuable asset in finding edge cases.
is applicable, it has been a valuable asset in finding edge cases.
[
SystemVerilog compliance suite
]:
https://github.com/
SymbiFlow
/sv-tests
[
SystemVerilog compliance suite
]:
https://github.com/
chipsalliance
/sv-tests
## Acknowledgements
## Acknowledgements
...
@@ -156,12 +159,11 @@ standard, his project was a great starting point.
...
@@ -156,12 +159,11 @@ standard, his project was a great starting point.
[
Tom Hawkin's Verilog parser
]:
https://github.com/tomahawkins/verilog
[
Tom Hawkin's Verilog parser
]:
https://github.com/tomahawkins/verilog
Reid Long was invaluable in developing this tool, providing significant tests
Reid Long was invaluable in developing this tool, providing significant tests
and advice, and isolating many bugs. His projects can be found
and advice, and isolating many bugs.
[
here
](
https://bitbucket.org/ReidLong/
)
.
Edric Kusuma helped me with the ins and outs of SystemVerilog, with which I had
Edric Kusuma helped me with the ins and outs of SystemVerilog, with which I had
no prior experience, and has also helped with test cases.
no prior experience, and has also helped with test cases.
Since sv2v's public release,
several
people have taken the time to file detailed
Since sv2v's public release,
many
people have taken the time to file detailed
bug reports and feature requests. I greatly appreciate their help in furthering
bug reports and feature requests. I greatly appreciate their help in furthering
the project.
the project.
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