support for gates with delays

src/Convert/Traverse.hs

@@ -630,14 +630,16 @@ traverseExprsM' strat exprMapper = moduleItemMapper
         return $ Instance m p' x r' l'
     moduleItemMapper (Modport x l) =
         mapM modportDeclMapper l >>= return . Modport x
-    moduleItemMapper (NInputGate  kw x lhs exprs) = do
+    moduleItemMapper (NInputGate  kw d x lhs exprs) = do
+        d' <- maybeExprMapper d
         exprs' <- mapM exprMapper exprs
         lhs' <- lhsMapper lhs
-        return $ NInputGate kw x lhs' exprs'
-    moduleItemMapper (NOutputGate kw x lhss expr) = do
+        return $ NInputGate kw d' x lhs' exprs'
+    moduleItemMapper (NOutputGate kw d x lhss expr) = do
+        d' <- maybeExprMapper d
         lhss' <- mapM lhsMapper lhss
         expr' <- exprMapper expr
-        return $ NOutputGate kw x lhss' expr'
+        return $ NOutputGate kw d' x lhss' expr'
     moduleItemMapper (Genvar   x) = return $ Genvar   x
     moduleItemMapper (Generate items) = do
         items' <- mapM (traverseNestedGenItemsM genItemMapper) items
@@ -769,12 +771,12 @@ traverseLHSsM' strat mapper item =
         traverseModuleItemLHSsM (Defparam lhs expr) = do
             lhs' <- mapper lhs
             return $ Defparam lhs' expr
-        traverseModuleItemLHSsM (NOutputGate kw x lhss expr) = do
+        traverseModuleItemLHSsM (NOutputGate kw d x lhss expr) = do
             lhss' <- mapM mapper lhss
-            return $ NOutputGate kw x lhss' expr
-        traverseModuleItemLHSsM (NInputGate  kw x lhs exprs) = do
+            return $ NOutputGate kw d x lhss' expr
+        traverseModuleItemLHSsM (NInputGate  kw d x lhs exprs) = do
             lhs' <- mapper lhs
-            return $ NInputGate kw x lhs' exprs
+            return $ NInputGate kw d x lhs' exprs
         traverseModuleItemLHSsM (AssertionItem (mx, a)) = do
             converted <-
                 traverseNestedStmtsM (traverseStmtLHSsM mapper) (Assertion a)

src/Language/SystemVerilog/AST/ModuleItem.hs

@@ -28,7 +28,7 @@ import Language.SystemVerilog.AST.Description (PackageItem)
 import Language.SystemVerilog.AST.Expr (Expr(Ident, Nil), Range, TypeOrExpr, showRanges)
 import Language.SystemVerilog.AST.GenItem (GenItem)
 import Language.SystemVerilog.AST.LHS (LHS)
-import Language.SystemVerilog.AST.Stmt (Stmt, AssertionItem)
+import Language.SystemVerilog.AST.Stmt (Stmt, AssertionItem, Timing(Delay))
 import Language.SystemVerilog.AST.Type (Identifier)
 
 data ModuleItem
@@ -43,8 +43,8 @@ data ModuleItem
     | Initial    Stmt
     | Final      Stmt
     | MIPackageItem PackageItem
-    | NInputGate  NInputGateKW  (Maybe Identifier)  LHS [Expr]
-    | NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr
+    | NInputGate  NInputGateKW  (Maybe Expr) Identifier  LHS [Expr]
+    | NOutputGate NOutputGateKW (Maybe Expr) Identifier [LHS] Expr
     | AssertionItem AssertionItem
     deriving Eq
 
@@ -58,8 +58,10 @@ instance Show ModuleItem where
     show (Modport     x l) = printf "modport %s(\n%s\n);" x (indent $ intercalate ",\n" $ map showModportDecl l)
     show (Initial     s  ) = printf "initial %s" (show s)
     show (Final       s  ) = printf   "final %s" (show s)
-    show (NInputGate  kw x lhs exprs) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs)
-    show (NOutputGate kw x lhss expr) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr)
+    show (NInputGate  kw d x lhs exprs) =
+        showGate kw d x $ show lhs : map show exprs
+    show (NOutputGate kw d x lhss expr) =
+        showGate kw d x $ (map show lhss) ++ [show expr]
     show (Assign d a b) =
         printf "assign %s%s = %s;" delayStr (show a) (show b)
         where delayStr = maybe "" (\e -> "#(" ++ show e ++ ") ") d
@@ -83,6 +85,13 @@ showPort (i, arg) =
         then show (fromJust arg)
         else printf ".%s(%s)" i (if isJust arg then show $ fromJust arg else "")
 
+showGate :: Show k => k -> Maybe Expr -> Identifier -> [String] -> String
+showGate kw d x args =
+    printf "%s %s%s(%s);" (show kw) delayStr nameStr (commas args)
+    where
+        delayStr = maybe "" (showPad . Delay) d
+        nameStr = showPad $ Ident x
+
 showParams :: [ParamBinding] -> String
 showParams params = indentedParenList $ map showParam params
 

src/Language/SystemVerilog/Parser/Parse.y

@@ -16,6 +16,7 @@ module Language.SystemVerilog.Parser.Parse (parse) where
 
 import Control.Monad.Except
 import Control.Monad.State
+import Data.Maybe (fromMaybe)
 import Language.SystemVerilog.AST
 import Language.SystemVerilog.Parser.ParseDecl
 import Language.SystemVerilog.Parser.Tokens
@@ -649,8 +650,8 @@ NonGenerateModuleItem :: { [ModuleItem] }
   | "genvar" Identifiers ";"             { map Genvar $2 }
   | "modport" ModportItems ";"           { map (uncurry Modport) $2 }
   | NonDeclPackageItem                   { map MIPackageItem $1 }
-  | NInputGateKW  NInputGates  ";"       { map (\(a, b, c) -> NInputGate  $1 a b c) $2 }
-  | NOutputGateKW NOutputGates ";"       { map (\(a, b, c) -> NOutputGate $1 a b c) $2 }
+  | NInputGateKW  NInputGates  ";"       { map (\(a, b, c, d) -> NInputGate  $1 a b c d) $2 }
+  | NOutputGateKW NOutputGates ";"       { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
   | AttributeInstance ModuleItem         { map (MIAttr $1) $2 }
   | AssertionItem                        { [AssertionItem $1] }
 
@@ -729,17 +730,17 @@ AttrSpec :: { AttrSpec }
   : Identifier "=" Expr { ($1, Just $3) }
   | Identifier          { ($1, Nothing) }
 
-NInputGates :: { [(Maybe Identifier, LHS, [Expr])] }
+NInputGates :: { [(Maybe Expr, Identifier, LHS, [Expr])] }
   : NInputGate                 { [$1] }
   | NInputGates "," NInputGate { $1 ++ [$3]}
-NOutputGates :: { [(Maybe Identifier, [LHS], Expr)] }
+NOutputGates :: { [(Maybe Expr, Identifier, [LHS], Expr)] }
   : NOutputGate                  { [$1] }
   | NOutputGates "," NOutputGate { $1 ++ [$3]}
 
-NInputGate :: { (Maybe Identifier, LHS, [Expr]) }
-  : opt(Identifier) "(" LHS "," Exprs ")" { ($1, $3, $5) }
-NOutputGate :: { (Maybe Identifier, [LHS], Expr) }
-  : opt(Identifier) "(" NOutputGateItems { ($1, fst $3, snd $3) }
+NInputGate :: { (Maybe Expr, Identifier, LHS, [Expr]) }
+  : opt(DelayControl) opt(Identifier) "(" LHS "," Exprs ")" { ($1, fromMaybe "" $2, $4, $6) }
+NOutputGate :: { (Maybe Expr, Identifier, [LHS], Expr) }
+  : opt(DelayControl) opt(Identifier) "(" NOutputGateItems { ($1, fromMaybe "" $2, fst $4, snd $4) }
 NOutputGateItems :: { ([LHS], Expr) }
   : Expr ")" { ([], $1) }
   | Expr "," NOutputGateItems { (fst $3 ++ [toLHS $1], snd $3) }

test/basic/gate.sv

+module top;
+    reg input_a;
+    reg input_b;
+
+    wire output_and;
+    wire output_and_delay;
+    wire output_not;
+    wire output_buf_delay;
+
+    and (output_and, input_a, input_b);
+    and #1 (output_and_delay, input_a, input_b);
+    not (output_not, input_a);
+    buf #2 foo_name (output_buf_delay, input_a);
+
+    initial repeat(2) begin
+        $monitor("%3d ", $time,
+            input_a, input_b,
+            output_and, output_and_delay,
+            output_not, output_buf_delay);
+
+        #1;
+        #1; input_a = 1;
+        #1; input_b = 0;
+        #1; input_b = 1;
+        #1;
+
+        #1; input_a = 0;
+        #1; input_b = 0;
+        #1; input_a = 0;
+        #1; input_b = 1;
+        #1; input_a = 1;
+        #1; input_b = 0;
+        #1; input_a = 1;
+        #1; input_b = 1;
+        #1;
+        #1;
+        #1;
+    end
+endmodule

test/basic/gate.v

+// This test is for parser coverge only.
+`include "gate.sv"