Commit 5ef24d2d by Zachary Snow

omit empty subroutine args list

parent b660cfbd
...@@ -76,7 +76,7 @@ instance Show Expr where ...@@ -76,7 +76,7 @@ instance Show Expr where
show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b) show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b)
show (Dot e n ) = printf "%s.%s" (show e) n show (Dot e n ) = printf "%s.%s" (show e) n
show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b) show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
show (Call ps f l) = printf "%s%s(%s)" (maybe "" (++ "::") ps) f (show l) show (Call ps f l) = printf "%s%s%s" (maybe "" (++ "::") ps) f (show l)
show (Cast tore e ) = printf "%s'(%s)" (showEither tore) (show e) show (Cast tore e ) = printf "%s'(%s)" (showEither tore) (show e)
show (DimsFn f v ) = printf "%s(%s)" (show f) (showEither v) show (DimsFn f v ) = printf "%s(%s)" (show f) (showEither v)
show (DimFn f v e) = printf "%s(%s, %s)" (show f) (showEither v) (show e) show (DimFn f v e) = printf "%s(%s, %s)" (show f) (showEither v) (show e)
...@@ -93,7 +93,7 @@ data Args ...@@ -93,7 +93,7 @@ data Args
deriving (Eq, Ord) deriving (Eq, Ord)
instance Show Args where instance Show Args where
show (Args pnArgs kwArgs) = commas strs show (Args pnArgs kwArgs) = "(" ++ (commas strs) ++ ")"
where where
strs = (map showPnArg pnArgs) ++ (map showKwArg kwArgs) strs = (map showPnArg pnArgs) ++ (map showKwArg kwArgs)
showPnArg = maybe "" show showPnArg = maybe "" show
......
...@@ -28,7 +28,7 @@ import Text.Printf (printf) ...@@ -28,7 +28,7 @@ import Text.Printf (printf)
import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad, showCase) import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad, showCase)
import Language.SystemVerilog.AST.Attr (Attr) import Language.SystemVerilog.AST.Attr (Attr)
import Language.SystemVerilog.AST.Decl (Decl) import Language.SystemVerilog.AST.Decl (Decl)
import Language.SystemVerilog.AST.Expr (Expr, Args) import Language.SystemVerilog.AST.Expr (Expr, Args(..))
import Language.SystemVerilog.AST.LHS (LHS) import Language.SystemVerilog.AST.LHS (LHS)
import Language.SystemVerilog.AST.Op (AsgnOp(AsgnOpEq)) import Language.SystemVerilog.AST.Op (AsgnOp(AsgnOpEq))
import Language.SystemVerilog.AST.Type (Identifier) import Language.SystemVerilog.AST.Type (Identifier)
...@@ -84,7 +84,8 @@ instance Show Stmt where ...@@ -84,7 +84,8 @@ instance Show Stmt where
where showInit (l, e) = showAssign (l, AsgnOpEq, e) where showInit (l, e) = showAssign (l, AsgnOpEq, e)
showAssign :: (LHS, AsgnOp, Expr) -> String showAssign :: (LHS, AsgnOp, Expr) -> String
showAssign (l, op, e) = printf "%s %s %s" (show l) (show op) (show e) showAssign (l, op, e) = printf "%s %s %s" (show l) (show op) (show e)
show (Subroutine ps x a) = printf "%s%s(%s);" (maybe "" (++ "::") ps) x (show a) show (Subroutine ps x a) = printf "%s%s%s;" (maybe "" (++ "::") ps) x aStr
where aStr = if a == Args [] [] then "" else show a
show (AsgnBlk o v e) = printf "%s %s %s;" (show v) (show o) (show e) show (AsgnBlk o v e) = printf "%s %s %s;" (show v) (show o) (show e)
show (Asgn t v e) = printf "%s <= %s%s;" (show v) (maybe "" showPad t) (show e) show (Asgn t v e) = printf "%s <= %s%s;" (show v) (maybe "" showPad t) (show e)
show (While e s) = printf "while (%s) %s" (show e) (show s) show (While e s) = printf "while (%s) %s" (show e) (show s)
......
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