Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
5de77ab6
Commit
5de77ab6
authored
Mar 26, 2019
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fix function and task input types
parent
edaff3dc
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
16 additions
and
5 deletions
+16
-5
src/Convert/Logic.hs
+10
-3
src/Language/SystemVerilog/Parser/Parse.y
+6
-2
No files found.
src/Convert/Logic.hs
View file @
5de77ab6
...
...
@@ -25,9 +25,17 @@ convert :: AST -> AST
convert
=
traverseDescriptions
convertDescription
convertDescription
::
Description
->
Description
convertDescription
(
orig
@
(
Part
_
Module
_
_
_
_
))
=
traverseModuleItems
(
traverseDecls
convertDecl
.
convertModuleItem
)
orig
convertDescription
orig
=
if
shouldConvert
then
traverseModuleItems
conversion
orig
else
orig
where
shouldConvert
=
case
orig
of
Part
_
Interface
_
_
_
_
->
False
Part
_
Module
_
_
_
_
->
True
PackageItem
_
->
True
Directive
_
->
False
conversion
=
traverseDecls
convertDecl
.
convertModuleItem
idents
=
execWriter
(
collectModuleItemsM
regIdents
orig
)
convertModuleItem
::
ModuleItem
->
ModuleItem
convertModuleItem
(
MIDecl
(
Variable
dir
(
IntegerVector
TLogic
sg
mr
)
ident
a
me
))
=
...
...
@@ -42,7 +50,6 @@ convertDescription (orig @ (Part _ Module _ _ _ _)) =
convertDecl
(
Variable
d
(
IntegerVector
TLogic
sg
rs
)
x
a
me
)
=
Variable
d
(
IntegerVector
TReg
sg
rs
)
x
a
me
convertDecl
other
=
other
convertDescription
other
=
other
regIdents
::
ModuleItem
->
Writer
RegIdents
()
regIdents
(
AlwaysC
_
stmt
)
=
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
5de77ab6
...
...
@@ -779,8 +779,12 @@ makeInput (Variable _ t x a me) = Variable Input t x a me
makeInput other = error $ "unexpected non-var decl: " ++ (show other)
defaultFuncInput :: Decl -> Decl
defaultFuncInput (Variable Input (Implicit sg rs) x a me) =
Variable Input (IntegerVector TLogic sg rs) x a me
defaultFuncInput (Variable dir (Implicit sg rs) x a me) =
Variable dir t x a me
where
t = if dir == Input || dir == Inout
then IntegerVector TLogic sg rs
else Implicit sg rs
defaultFuncInput other = other
combineTags :: Maybe Identifier -> Maybe Identifier -> Maybe Identifier
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment