Commit 5c8d838e by Zachary Snow

fix overzealous task/function decl hoisting

parent b8759776
......@@ -8,7 +8,7 @@
module Convert.TFBlock (convert) where
import Data.List (isPrefixOf)
import Data.List (intersect, isPrefixOf)
import Convert.Traverse
import Language.SystemVerilog.AST
......@@ -41,15 +41,35 @@ stmtsToStmt stmts = Block Seq "" [] stmts
flattenOuterBlocks :: Stmt -> ([Decl], [Stmt])
flattenOuterBlocks (Block Seq "" declsA [stmt]) =
(declsA ++ declsB, stmtsB)
if canCombine declsA declsB
then (declsA ++ declsB, stmtsB)
else (declsA, [stmt])
where (declsB, stmtsB) = flattenOuterBlocks stmt
flattenOuterBlocks (Block Seq "" declsA (Block Seq name declsB stmtsA : stmtsB)) =
flattenOuterBlocks $ Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
if canCombine declsA declsB
then flattenOuterBlocks $
Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
else (declsA, Block Seq name declsB stmtsA : stmtsB)
flattenOuterBlocks (Block Seq name decls stmts)
| notscope name = (decls, stmts)
| otherwise = ([], [Block Seq name decls stmts])
flattenOuterBlocks stmt = ([], [stmt])
canCombine :: [Decl] -> [Decl] -> Bool
canCombine [] _ = True
canCombine _ [] = True
canCombine declsA declsB =
null $ intersect (declNames declsA) (declNames declsB)
declNames :: [Decl] -> [Identifier]
declNames = filter (not . null) . map declName
declName :: Decl -> Identifier
declName (Variable _ _ x _ _) = x
declName (Param _ _ x _) = x
declName (ParamType _ x _) = x
declName CommentDecl{} = ""
notscope :: Identifier -> Bool
notscope "" = True
notscope name = "sv2v_autoblock_" `isPrefixOf` name
`define TEST \
reg x; \
begin \
reg [1:0] x; \
$display("%0d %b", $bits(x), x); \
end \
$display("%0d %b", $bits(x), x);
module top;
task t;
input integer unused;
`TEST
endtask
function f;
input integer unused;
`TEST
endfunction
initial t(f(0));
initial begin
`TEST
end
endmodule
module top;
initial begin : blk
integer i;
reg [1:0] y;
reg x;
for (i = 0; i < 3; i = i + 1) begin
$display("%0d %b", 2, y);
$display("%0d %b", 1, x);
end
end
endmodule
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