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lvzhengyang
sv2v
Commits
5c0f414d
Commit
5c0f414d
authored
Dec 03, 2020
by
Zachary Snow
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convert wildcard bindings before interfaces
parent
091520e4
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3 changed files
with
33 additions
and
1 deletions
+33
-1
src/Convert.hs
+1
-1
test/basic/interface_star.sv
+21
-0
test/basic/interface_star.v
+11
-0
No files found.
src/Convert.hs
View file @
5c0f414d
...
...
@@ -75,7 +75,6 @@ phases excludes =
,
Convert
.
ParamType
.
convert
,
Convert
.
SizeCast
.
convert
,
Convert
.
Simplify
.
convert
,
Convert
.
StarPort
.
convert
,
Convert
.
Stream
.
convert
,
Convert
.
Struct
.
convert
,
Convert
.
TFBlock
.
convert
...
...
@@ -94,6 +93,7 @@ phases excludes =
,
Convert
.
Foreach
.
convert
,
Convert
.
StringParam
.
convert
,
selectExclude
(
Job
.
Interface
,
Convert
.
Interface
.
convert
)
,
Convert
.
StarPort
.
convert
,
selectExclude
(
Job
.
Always
,
Convert
.
AlwaysKW
.
convert
)
,
selectExclude
(
Job
.
Succinct
,
Convert
.
RemoveComments
.
convert
)
]
...
...
test/basic/interface_star.sv
0 → 100644
View file @
5c0f414d
interface
Interface
(
data
)
;
input
logic
data
;
initial
#
1
$
display
(
"Interface %b"
,
data
)
;
endinterface
module
Module
(
intf
)
;
Interface
intf
;
initial
#
2
$
display
(
"Module %b"
,
intf
.
data
)
;
endmodule
module
top
;
logic
data
;
Interface
intf
(
.*
)
;
Module
m
(
.*
)
;
initial
begin
data
=
0
;
#
1
;
data
=
1
;
#
1
;
end
endmodule
test/basic/interface_star.v
0 → 100644
View file @
5c0f414d
module
top
;
reg
data
;
initial
#
1
$
display
(
"Interface %b"
,
data
)
;
initial
#
2
$
display
(
"Module %b"
,
data
)
;
initial
begin
data
=
0
;
#
1
;
data
=
1
;
#
1
;
end
endmodule
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