fix dev iverilog test incompatibilities

test/core/cast_top_item_tb.v

 module top;
     genvar i;
     generate
-        for (i = 0; i < 32; i = i + 1)
+        for (i = 1; i < 32; i = i + 1)
             mod #(i) m();
     endgenerate
 endmodule

test/core/delay.sv

@@ -9,6 +9,6 @@ module top;
         #1;
         #10; a = 'h5;
         #10;
-        $finish;
+        $finish(0);
     end
 endmodule

test/core/delay.v

@@ -9,6 +9,6 @@ module top;
         #1;
         #10; a = 'h5;
         #10;
-        $finish;
+        $finish(0);
     end
 endmodule

test/core/interface_bundle.sv

@@ -35,6 +35,6 @@ module top;
     initial begin
         $monitor("%b %b %b %b", b.index, b.clock, b.inp, b.out);
         #100;
-        $finish;
+        $finish(0);
     end
 endmodule

test/core/interface_bundle.v

@@ -23,7 +23,7 @@ module impl;
     initial begin
         $monitor("%b %b %b %b", b_index, b_clock, b_inp, b_out);
         #100;
-        $finish;
+        $finish(0);
     end
 endmodule
 

test/core/interface_generate.sv

@@ -48,6 +48,6 @@ module top;
 
     initial begin
         $monitor("%0d %b %b", $time, clock, intf.req);
-        #100 $finish;
+        #100 $finish(0);
     end
 endmodule

test/core/interface_generate.v

@@ -52,6 +52,6 @@ module top;
 
     initial begin
         $monitor("%0d %b %b", $time, clock, intf.req);
-        #100 $finish;
+        #100 $finish(0);
     end
 endmodule

test/core/jump.sv

@@ -112,7 +112,7 @@ module top;
             break;
             $display("UNREACHABLE ", `__LINE__);
         end
-    initial #5 $finish;
+    initial #5 $finish(0);
 
     initial begin
         for (int unsigned i = 0; i < 5; ++i) begin

test/core/jump.v

@@ -87,7 +87,7 @@ module top;
             i = 10;
         end
     end
-    initial #5 $finish;
+    initial #5 $finish(0);
 
     initial begin : loops_de
         reg unsigned [31:0] i;