Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
5b336439
Commit
5b336439
authored
Feb 09, 2019
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
cleanup of port decl parsing
parent
ebd7ae67
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
58 additions
and
83 deletions
+58
-83
Language/SystemVerilog/Parser/Parse.y
+58
-83
No files found.
Language/SystemVerilog/Parser/Parse.y
View file @
5b336439
...
@@ -5,6 +5,7 @@ import Data.Bits
...
@@ -5,6 +5,7 @@ import Data.Bits
import Data.List
import Data.List
import Data.BitVec
import Data.BitVec
import Data.Maybe
import Language.SystemVerilog.AST
import Language.SystemVerilog.AST
import Language.SystemVerilog.Parser.Tokens
import Language.SystemVerilog.Parser.Tokens
}
}
...
@@ -151,62 +152,56 @@ string { Token Lit_string _ _ }
...
@@ -151,62 +152,56 @@ string { Token Lit_string _ _ }
%%
%%
opt(p) :: { Maybe a }
: p { Just $1 }
| { Nothing }
Modules :: { [Module] }
Modules :: { [Module] }
:
{ [] }
: {- empty -}
{ [] }
| Modules Module { $1 ++ [$2] }
| Modules Module { $1 ++ [$2] }
Module :: { Module }
Module :: { Module }
: "module" Identifier ModulePortList ";" ModuleItems "endmodule"{ Module $2 $3 $5 }
: "module" Identifier ";" ModuleItems "endmodule" { Module $2 [] $4 }
| "module" Identifier ListOfPortDeclarations ";" ModuleItems "endmodule" { uncurry (Module $2) $ combinePortDeclsAndModuleItems $3 $5 }
| "module" Identifier PortNames ";" ModuleItems "endmodule" { Module $2 $3 $5 }
| "module" Identifier PortDecls ";" ModuleItems "endmodule" { Module $2 (getPortNames $3) ($3 ++ $5) }
Identifier :: { Identifier }
Identifier :: { Identifier }
: simpleIdentifier
{ tokenString $1 }
: simpleIdentifier
{ tokenString $1 }
| escapedIdentifier
{ tokenString $1 }
| escapedIdentifier
{ tokenString $1 }
| systemIdentifier
{ tokenString $1 }
| systemIdentifier
{ tokenString $1 }
ModulePortList :: { [Identifier] }
Identifiers :: { [Identifier] }
: { [] }
: Identifier { [$1] }
| "(" ")" { [] }
| Identifiers "," Identifier { $1 ++ [$3] }
| "(" ModulePortList1 ")" { $2 }
PortNames :: { [Identifier] }
ModulePortList1 :: { [Identifier] }
: "(" Identifiers ")" { $2 }
: Identifier { [$1] }
| ModulePortList1 "," Identifier { $1 ++ [$3] }
-- abuses delimiter propogation hack to avoid conflicts
PortDecls :: { [ModuleItem] }
: "(" PortDeclsFollow { $2 }
PortDeclsFollow :: { [ModuleItem] }
: ")" { [] }
| PortDecl(")") { $1 }
| PortDecl(",") PortDeclsFollow { $1 ++ $2 }
PortDecl(delim) :: { [ModuleItem] }
: "inout" opt(NetType) opt(Range) Identifiers delim { portDeclToModuleItems Inout $2 $3 (zip $4 (repeat Nothing)) }
| "input" opt(NetType) opt(Range) Identifiers delim { portDeclToModuleItems Input $2 $3 (zip $4 (repeat Nothing)) }
| "output" opt(NetType) opt(Range) Identifiers delim { portDeclToModuleItems Output $2 $3 (zip $4 (repeat Nothing)) }
| "output" "reg" opt(Range) VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Reg) $3 $4 }
VariablePortIdentifiers :: { [(Identifier, Maybe Expr)] }
: VariablePortIdentifier { [$1] }
| VariablePortIdentifiers "," VariablePortIdentifier { $1 ++ [$3] }
VariablePortIdentifier :: { (Identifier, Maybe Expr) }
: Identifier { ($1, Nothing) }
| Identifier "=" Expr { ($1, Just $3) }
ModuleItems :: { [ModuleItem] }
ModuleItems :: { [ModuleItem] }
: { [] }
: { [] }
| ModuleItems ModuleItem { $1 ++ $2 }
| ModuleItems ModuleItem { $1 ++ $2 }
ListOfPortDeclarations
: "(" PortDeclarations ")" { $2 }
PortDeclarations
: PortDeclaration { [$1] }
| PortDeclaration2 PortDeclarations { $1 : $2 }
PortDeclaration2 :: { (Direction, Either Type (Maybe Range), [(Identifier, Maybe Expr)]) }
: "inout" opt(NetType) opt(Range) Identifiers "," { toPortDeclaration Inout $2 $3 $4 }
| "input" opt(NetType) opt(Range) Identifiers "," { toPortDeclaration Input $2 $3 $4 }
| "output" opt(NetType) opt(Range) Identifiers "," { toPortDeclaration Output $2 $3 $4 }
| "output" "reg" opt(Range) VarPortIdentifiers "," { (Output, Left (Reg $3), $4) }
PortDeclaration :: { (Direction, Either Type (Maybe Range), [(Identifier, Maybe Expr)]) }
: "inout" opt(NetType) opt(Range) Identifiers { toPortDeclaration Inout $2 $3 $4 }
| "input" opt(NetType) opt(Range) Identifiers { toPortDeclaration Input $2 $3 $4 }
| "output" opt(NetType) opt(Range) Identifiers { toPortDeclaration Output $2 $3 $4 }
| "output" "reg" opt(Range) VarPortIdentifiers { (Output, Left (Reg $3), $4) }
VarPortIdentifiers :: { [(Identifier, Maybe Expr)] }
: VarPortIdentifier { [$1] }
| VarPortIdentifiers "," VarPortIdentifier { $1 ++ [$3] }
VarPortIdentifier :: { (Identifier, Maybe Expr) }
: Identifier { ($1, Nothing) }
| Identifier "=" Expr { ($1, Just $3) }
opt(p) : p { Just $1 }
| { Nothing }
NetType
NetType
: "wire" { Wire }
: "wire" { Wire }
...
@@ -218,7 +213,7 @@ MaybeTypeOrRange :: { Either Type (Maybe Range) }
...
@@ -218,7 +213,7 @@ MaybeTypeOrRange :: { Either Type (Maybe Range) }
ModuleItem :: { [ModuleItem] }
ModuleItem :: { [ModuleItem] }
: "parameter" MaybeRange Identifier "=" Expr ";" { [Parameter $2 $3 $5] }
: "parameter" MaybeRange Identifier "=" Expr ";" { [Parameter $2 $3 $5] }
| "localparam" MaybeRange Identifier "=" Expr ";" { [Localparam $2 $3 $5] }
| "localparam" MaybeRange Identifier "=" Expr ";" { [Localparam $2 $3 $5] }
| PortDecl
aration ";" { portDeclToModuleItems
$1 }
| PortDecl
(";") {
$1 }
| "reg" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Reg $2) $3 }
| "reg" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Reg $2) $3 }
| "wire" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
| "wire" MaybeRange WireDeclarations ";" { map (uncurry $ LocalNet $ Wire $2) $3 }
| "integer" Identifiers ";" { [Integer $2] }
| "integer" Identifiers ";" { [Integer $2] }
...
@@ -228,10 +223,6 @@ ModuleItem :: { [ModuleItem] }
...
@@ -228,10 +223,6 @@ ModuleItem :: { [ModuleItem] }
| "always" "@" "(" Sense ")" Stmt { [Always (Just $4) $6] }
| "always" "@" "(" Sense ")" Stmt { [Always (Just $4) $6] }
| Identifier ParameterBindings Identifier Bindings ";" { [Instance $1 $2 $3 $4] }
| Identifier ParameterBindings Identifier Bindings ";" { [Instance $1 $2 $3 $4] }
Identifiers :: { [Identifier] }
: Identifier { [$1] }
| Identifiers "," Identifier { $1 ++ [$3] }
RegDeclarations :: { [(Identifier, Maybe Range)] }
RegDeclarations :: { [(Identifier, Maybe Range)] }
: Identifier MaybeRange { [($1, $2)] }
: Identifier MaybeRange { [($1, $2)] }
| RegDeclarations "," Identifier MaybeRange { $1 ++ [($3, $4)] }
| RegDeclarations "," Identifier MaybeRange { $1 ++ [($3, $4)] }
...
@@ -400,48 +391,32 @@ toNumber = number . tokenString
...
@@ -400,48 +391,32 @@ toNumber = number . tokenString
| otherwise = error $ "Invalid number format: " ++ a
| otherwise = error $ "Invalid number format: " ++ a
toPortDeclaration
portDeclToModuleItems
:: Direction
:: Direction
-> (Maybe ((Maybe Range) -> Type))
-> (Maybe ((Maybe Range) -> Type))
-> Maybe Range
-> Maybe Range
-> [Identifier]
-> [(Identifier, Maybe Expr)]
-> (Direction, Either Type (Maybe Range), [(Identifier, Maybe Expr)])
-> [ModuleItem]
toPortDeclaration dir tfm mr ids =
portDeclToModuleItems dir Nothing mr l =
(dir, t, vals)
map (PortDecl dir mr) $ map toIdentifier $ l
where
t =
case tfm of
Nothing -> Right mr
Just tf -> Left (tf mr)
vals = zip ids (repeat Nothing)
portDeclToModuleItems :: (Direction, Either Type (Maybe Range), [(Identifier, Maybe Expr)]) -> [ModuleItem]
portDeclToModuleItems (dir, Right r, l) =
map (PortDecl dir r) $ map toIdentifier $ l
where
where
toIdentifier (x, Just _) = error "Incomplete port decl cannot have initialization"
toIdentifier (x, Just _) = error "
ParseError:
Incomplete port decl cannot have initialization"
toIdentifier (x, Nothing) = x
toIdentifier (x, Nothing) = x
portDeclToModuleItems (dir, Left t, l) =
portDeclToModuleItems dir (Just tf) mr l =
foldr (++) [] $
concat $ map toItems l
map toItems l
where
where
r = case t of
Reg mr -> mr
Wire mr -> mr
toItems (x, e) =
toItems (x, e) =
[ PortDecl dir r x
[ PortDecl dir
m
r x
, LocalNet
t
x e ]
, LocalNet
(tf mr)
x e ]
combinePortDeclsAndModuleItems
getPortNames :: [ModuleItem] -> [Identifier]
:: [(Direction, Either Type (Maybe Range), [(Identifier, Maybe Expr)])]
getPortNames items =
-> [ModuleItem]
mapMaybe getPortName items
-> ([Identifier], [ModuleItem])
combinePortDeclsAndModuleItems portDecls items =
(declIdents, declItems ++ items)
where
where
declIdents = concat $ map (\(_, _, idsAndExprs) -> map fst idsAndExprs) portDecls
getPortName :: ModuleItem -> Maybe Identifier
declItems = concat $ map portDeclToModuleItems portDecls
getPortName (PortDecl _ _ ident) = Just ident
getPortName _ = Nothing
}
}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment