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lvzhengyang
sv2v
Commits
5a8801a4
Commit
5a8801a4
authored
Apr 23, 2021
by
Zachary Snow
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allow trailing commas in parameter and port lists and bindings
parent
bdc7b5ad
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4 changed files
with
40 additions
and
4 deletions
+40
-4
src/Language/SystemVerilog/Parser/Parse.y
+7
-4
src/Language/SystemVerilog/Parser/ParseDecl.hs
+8
-0
test/basic/trailing_commas.sv
+13
-0
test/basic/trailing_commas.v
+12
-0
No files found.
src/Language/SystemVerilog/Parser/Parse.y
View file @
5a8801a4
...
...
@@ -579,14 +579,17 @@ PIParams :: { [Decl] }
|
"#"
"("
")"
{
[]
}
|
"#"
"("
ParamsFollow
{
$
3
}
ParamsFollow
::
{
[
Decl
]
}
:
ParamAsgn
")"
{
[
$
1
]
}
:
ParamAsgn
ParamsEnd
{
[
$
1
]
}
|
ParamAsgn
","
ParamsFollow
{
$
1
:
$
3
}
|
ParamsDecl
{
$
1
}
ParamsDecl
::
{
[
Decl
]
}
:
ModuleParameterDecl
(
")"
)
{
$
1
}
:
ModuleParameterDecl
(
ParamsEnd
)
{
$
1
}
|
ModuleParameterDecl
(
","
)
ParamsDecl
{
$
1
++
$
2
}
ParamAsgn
::
{
Decl
}
:
Identifier
"="
Expr
{
Param
Parameter
(
Implicit
Unspecified
[]
)
$
1
$
3
}
ParamsEnd
:
")"
{}
|
","
")"
{}
PortDecls
::
{
([
Identifier
],
[
ModuleItem
])
}
:
"("
PortDeclTokens
(
")"
)
{
parseDTsAsPortDecls
$
2
}
...
...
@@ -965,7 +968,7 @@ PortBindings :: { [PortBinding] }
:
"("
")"
{
[]
}
|
"("
PortBindingsInside
")"
{
$
2
}
PortBindingsInside
::
{
[
PortBinding
]
}
:
PortBinding
{
[
$
1
]
}
:
PortBinding
opt
(
","
)
{
[
$
1
]
}
|
PortBinding
","
PortBindingsInside
{
$
1
:
$
3
}
PortBinding
::
{
PortBinding
}
:
"."
Identifier
"("
ExprOrNil
")"
{
(
$
2
,
$
4
)
}
...
...
@@ -977,7 +980,7 @@ ParamBindings :: { [ParamBinding] }
:
"#"
"("
")"
{
[]
}
|
"#"
"("
ParamBindingsInside
")"
{
$
3
}
ParamBindingsInside
::
{
[
ParamBinding
]
}
:
ParamBinding
{
[
$
1
]
}
:
ParamBinding
opt
(
","
)
{
[
$
1
]
}
|
ParamBinding
","
ParamBindingsInside
{
$
1
:
$
3
}
ParamBinding
::
{
ParamBinding
}
:
"."
Identifier
"("
TypeOrExpr
")"
{
(
$
2
,
$
4
)
}
...
...
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
5a8801a4
...
...
@@ -91,6 +91,14 @@ forbidNonEqAsgn tokens =
-- Example: `input foo, bar, One inst`
parseDTsAsPortDecls
::
[
DeclToken
]
->
([
Identifier
],
[
ModuleItem
])
parseDTsAsPortDecls
pieces
=
parseDTsAsPortDecls'
$
case
last
pieces
of
DTComma
{}
->
init
pieces
_
->
pieces
-- internal parseDTsAsPortDecls after the removal of an optional trailing comma
parseDTsAsPortDecls'
::
[
DeclToken
]
->
([
Identifier
],
[
ModuleItem
])
parseDTsAsPortDecls'
pieces
=
forbidNonEqAsgn
pieces
$
if
isSimpleList
then
(
simpleIdents
,
[]
)
...
...
test/basic/trailing_commas.sv
0 → 100644
View file @
5a8801a4
module
ModuleA
#(
P
=
1
,
)
(
inp
,
)
;
input
inp
;
initial
$
display
(
"ModuleA P=%0d inp=%b"
,
P
,
inp
)
;
endmodule
module
ModuleB
#(
parameter
P
,
)
(
input
inp
,
)
;
initial
$
display
(
"ModuleB P=%0d inp=%b"
,
P
,
inp
)
;
endmodule
module
top
;
ModuleA
#(
1
,
)
a
(
1'b1
,
)
;
ModuleB
#(
.
P
(
1
)
,
)
b
(
.
inp
(
1'b1
)
,
)
;
endmodule
test/basic/trailing_commas.v
0 → 100644
View file @
5a8801a4
module
ModuleA
#(
parameter
P
=
1
)
(
input
inp
)
;
initial
$
display
(
"ModuleA P=%0d inp=%b"
,
P
,
inp
)
;
endmodule
module
ModuleB
#(
parameter
P
=
0
)
(
input
inp
)
;
initial
$
display
(
"ModuleB P=%0d inp=%b"
,
P
,
inp
)
;
endmodule
module
top
;
ModuleA
#(
1
)
a
(
1'b1
)
;
ModuleB
#(
.
P
(
1
))
b
(
.
inp
(
1'b1
))
;
endmodule
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