elaborate `wire integer` to `wire signed [31:0]`

src/Convert/IntTypes.hs

@@ -16,12 +16,18 @@ convertModuleItem :: ModuleItem -> ModuleItem
 convertModuleItem = traverseNodes
     traverseExpr traverseDecl traverseType traverseLHS traverseStmt
     where
-        traverseDecl = traverseDeclNodes traverseType traverseExpr
         traverseLHS = traverseNestedLHSs $ traverseLHSExprs traverseExpr
         traverseStmt = traverseNestedStmts $
             traverseStmtDecls (traverseDeclNodes traverseType id) .
             traverseStmtExprs traverseExpr
 
+traverseDecl :: Decl -> Decl
+traverseDecl (Net d n s t x a e) =
+    traverseDeclNodes traverseType traverseExpr $
+        Net d n s (convertTypeForce t) x a e
+traverseDecl decl =
+    traverseDeclNodes traverseType traverseExpr decl
+
 traverseType :: Type -> Type
 traverseType =
     traverseSinglyNestedTypes traverseType .
@@ -47,20 +53,20 @@ convertType other = other
 
 convertStructFields :: [(Type, Identifier)] -> [(Type, Identifier)]
 convertStructFields fields =
-    zip (map (convertStructFieldType . fst) fields) (map snd fields)
+    zip (map (convertTypeForce . fst) fields) (map snd fields)
 
-convertStructFieldType :: Type -> Type
-convertStructFieldType (IntegerAtom TInteger sg) = IntegerAtom TInt sg
-convertStructFieldType t = t
+convertTypeForce :: Type -> Type
+convertTypeForce (IntegerAtom TInteger sg) = IntegerAtom TInt sg
+convertTypeForce t = t
 
 convertExpr :: Expr -> Expr
 convertExpr (Pattern items) =
     Pattern $ zip names exprs
     where
-        names = map (convertPatternTypeOrExpr . fst) items
+        names = map (convertTypeOrExprForce . fst) items
         exprs = map snd items
 convertExpr other = other
 
-convertPatternTypeOrExpr :: TypeOrExpr -> TypeOrExpr
-convertPatternTypeOrExpr (Left t) = Left $ convertStructFieldType t
-convertPatternTypeOrExpr (Right e) = Right e
+convertTypeOrExprForce :: TypeOrExpr -> TypeOrExpr
+convertTypeOrExprForce (Left t) = Left $ convertTypeForce t
+convertTypeOrExprForce (Right e) = Right e

test/core/net_base_type.sv

+`ifdef REF
+    `define TEST(kw, name, conv) \
+        wire conv wire_``name = 1'sb1; \
+        wire [63:0] wire_``name``_ext = wire_``name;
+`else
+    `define TEST(kw, name, conv) \
+        wire kw wire_``name = 1'sb1; \
+        wire [63:0] wire_``name``_ext = wire_``name;
+`endif
+
+module top;
+    `TEST(reg, reg, )
+    `TEST(bit, bit, )
+    `TEST(logic, logic, )
+    `TEST(integer, integer, signed [31:0])
+    `TEST(int, int, signed [31:0])
+    `TEST(shortint, shortint, signed [15:0])
+    `TEST(byte, byte, signed [7:0])
+    `TEST(integer unsigned, integer_unsigned, [31:0])
+    `TEST(int unsigned, int_unsigned, [31:0])
+    `TEST(shortint unsigned, shortint_unsigned, [15:0])
+    `TEST(byte unsigned, byte_unsigned, [7:0])
+endmodule

test/core/net_base_type.v

+`define REF
+`include "net_base_type.sv"