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lvzhengyang
sv2v
Commits
4ded2a59
Commit
4ded2a59
authored
Aug 15, 2021
by
Zachary Snow
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apply implicit port directions to tasks and functions
parent
61ccf3cb
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3 changed files
with
59 additions
and
18 deletions
+59
-18
src/Language/SystemVerilog/Parser/ParseDecl.hs
+19
-18
test/core/task_implicit_dir.sv
+19
-0
test/core/task_implicit_dir.v
+21
-0
No files found.
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
4ded2a59
...
@@ -101,23 +101,6 @@ parseDTsAsPortDecls' pieces =
...
@@ -101,23 +101,6 @@ parseDTsAsPortDecls' pieces =
pieces'
=
filter
(
not
.
isAttr
)
pieces
pieces'
=
filter
(
not
.
isAttr
)
pieces
propagateDirections
::
Direction
->
[
Decl
]
->
[
Decl
]
propagateDirections
dir
(
decl
@
(
Variable
_
InterfaceT
{}
_
_
_
)
:
decls
)
=
decl
:
propagateDirections
dir
decls
propagateDirections
lastDir
(
Variable
currDir
t
x
a
e
:
decls
)
=
decl
:
propagateDirections
dir
decls
where
decl
=
Variable
dir
t
x
a
e
dir
=
if
currDir
==
Local
then
lastDir
else
currDir
propagateDirections
lastDir
(
Net
currDir
n
s
t
x
a
e
:
decls
)
=
decl
:
propagateDirections
dir
decls
where
decl
=
Net
dir
n
s
t
x
a
e
dir
=
if
currDir
==
Local
then
lastDir
else
currDir
propagateDirections
dir
(
decl
:
decls
)
=
decl
:
propagateDirections
dir
decls
propagateDirections
_
[]
=
[]
portNames
::
[
Decl
]
->
[
Identifier
]
portNames
::
[
Decl
]
->
[
Identifier
]
portNames
=
filter
(
not
.
null
)
.
map
portName
portNames
=
filter
(
not
.
null
)
.
map
portName
portName
::
Decl
->
Identifier
portName
::
Decl
->
Identifier
...
@@ -141,6 +124,24 @@ parseDTsAsPortDecls' pieces =
...
@@ -141,6 +124,24 @@ parseDTsAsPortDecls' pieces =
wrapDecl
::
[
Attr
]
->
Decl
->
ModuleItem
wrapDecl
::
[
Attr
]
->
Decl
->
ModuleItem
wrapDecl
attrs
decl
=
foldr
MIAttr
(
MIPackageItem
$
Decl
decl
)
attrs
wrapDecl
attrs
decl
=
foldr
MIAttr
(
MIPackageItem
$
Decl
decl
)
attrs
-- internal utility for carying forward port directions in a port list
propagateDirections
::
Direction
->
[
Decl
]
->
[
Decl
]
propagateDirections
dir
(
decl
@
(
Variable
_
InterfaceT
{}
_
_
_
)
:
decls
)
=
decl
:
propagateDirections
dir
decls
propagateDirections
lastDir
(
Variable
currDir
t
x
a
e
:
decls
)
=
decl
:
propagateDirections
dir
decls
where
decl
=
Variable
dir
t
x
a
e
dir
=
if
currDir
==
Local
then
lastDir
else
currDir
propagateDirections
lastDir
(
Net
currDir
n
s
t
x
a
e
:
decls
)
=
decl
:
propagateDirections
dir
decls
where
decl
=
Net
dir
n
s
t
x
a
e
dir
=
if
currDir
==
Local
then
lastDir
else
currDir
propagateDirections
dir
(
decl
:
decls
)
=
decl
:
propagateDirections
dir
decls
propagateDirections
_
[]
=
[]
-- internal utility for a simple list of port identifiers
-- internal utility for a simple list of port identifiers
parseDTsAsIdents
::
[
DeclToken
]
->
Maybe
[
Identifier
]
parseDTsAsIdents
::
[
DeclToken
]
->
Maybe
[
Identifier
]
parseDTsAsIdents
[
DTIdent
_
x
,
DTEnd
_
_
]
=
Just
[
x
]
parseDTsAsIdents
[
DTIdent
_
x
,
DTEnd
_
_
]
=
Just
[
x
]
...
@@ -235,7 +236,7 @@ parseDTsAsIntantiation l0 delimTok =
...
@@ -235,7 +236,7 @@ parseDTsAsIntantiation l0 delimTok =
-- [PUBLIC]: parser for comma-separated task/function port declarations
-- [PUBLIC]: parser for comma-separated task/function port declarations
parseDTsAsTFDecls
::
[
DeclToken
]
->
[
Decl
]
parseDTsAsTFDecls
::
[
DeclToken
]
->
[
Decl
]
parseDTsAsTFDecls
=
parseDTsAsDecls
ModeDefault
parseDTsAsTFDecls
=
p
ropagateDirections
Input
.
p
arseDTsAsDecls
ModeDefault
-- [PUBLIC]; used for "single" declarations, i.e., declarations appearing
-- [PUBLIC]; used for "single" declarations, i.e., declarations appearing
...
...
test/core/task_implicit_dir.sv
0 → 100644
View file @
4ded2a59
module
top
;
task
t
(
integer
inp
,
output
byte
out1
,
shortint
out2
)
;
$
display
(
"t(inp = %0d)"
,
inp
)
;
out1
=
inp
;
out2
=
inp
;
endtask
initial
begin
integer
a
;
byte
b
;
shortint
c
;
a
=
5
;
t
(
a
,
b
,
c
)
;
$
display
(
"a = %0d, b = %0d, c = %0d"
,
a
,
b
,
c
)
;
end
endmodule
test/core/task_implicit_dir.v
0 → 100644
View file @
4ded2a59
module
top
;
task
t
(
input
reg
[
31
:
0
]
inp
,
output
reg
[
7
:
0
]
out1
,
output
reg
[
15
:
0
]
out2
)
;
begin
$
display
(
"t(inp = %0d)"
,
inp
)
;
out1
=
inp
;
out2
=
inp
;
end
endtask
initial
begin
:
blk
reg
[
31
:
0
]
a
;
reg
[
7
:
0
]
b
;
reg
[
15
:
0
]
c
;
a
=
5
;
t
(
a
,
b
,
c
)
;
$
display
(
"a = %0d, b = %0d, c = %0d"
,
a
,
b
,
c
)
;
end
endmodule
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