added support for other procedural loops

src/Convert/Traverse.hs

@@ -123,6 +123,10 @@ traverseNestedStmtsM mapper = fullMapper
         cs (AsgnBlk lhs expr) = return $ AsgnBlk lhs expr
         cs (Asgn    lhs expr) = return $ Asgn    lhs expr
         cs (For a b c stmt) = fullMapper stmt >>= return . For a b c
+        cs (While   e stmt) = fullMapper stmt >>= return . While   e
+        cs (RepeatL e stmt) = fullMapper stmt >>= return . RepeatL e
+        cs (DoWhile e stmt) = fullMapper stmt >>= return . DoWhile e
+        cs (Forever   stmt) = fullMapper stmt >>= return . Forever
         cs (If e s1 s2) = do
             s1' <- fullMapper s1
             s2' <- fullMapper s2
@@ -239,6 +243,13 @@ traverseExprsM mapper = moduleItemMapper
         e2' <- exprMapper e2
         cc' <- exprMapper cc
         return $ For (x1, e1') cc' (x2, e2') stmt
+    flatStmtMapper (While   e stmt) =
+        exprMapper e >>= \e' -> return $ While   e' stmt
+    flatStmtMapper (RepeatL e stmt) =
+        exprMapper e >>= \e' -> return $ RepeatL e' stmt
+    flatStmtMapper (DoWhile e stmt) =
+        exprMapper e >>= \e' -> return $ DoWhile e' stmt
+    flatStmtMapper (Forever   stmt) = return $ Forever stmt
     flatStmtMapper (If cc s1 s2) =
         exprMapper cc >>= \cc' -> return $ If cc' s1 s2
     flatStmtMapper (Timing event stmt) = return $ Timing event stmt

src/Language/SystemVerilog/AST.hs

@@ -400,6 +400,10 @@ data Stmt
   | For     (Identifier, Expr) Expr (Identifier, Expr) Stmt
   | AsgnBlk LHS Expr
   | Asgn    LHS Expr
+  | While   Expr Stmt
+  | RepeatL Expr Stmt
+  | DoWhile Expr Stmt
+  | Forever Stmt
   | If      Expr Stmt Stmt
   | Timing  Timing Stmt
   | Return  Expr
@@ -429,6 +433,10 @@ instance Show Stmt where
   show (For (a,b) c (d,e) f) = printf "for (%s = %s; %s; %s = %s)\n%s" a (show b) (show c) d (show e) $ indent $ show f
   show (AsgnBlk v e) = printf "%s = %s;"  (show v) (show e)
   show (Asgn    v e) = printf "%s <= %s;" (show v) (show e)
+  show (While   e s) = printf  "while (%s) %s" (show e) (show s)
+  show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
+  show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
+  show (Forever s  ) = printf "forever %s" (show s)
   show (If a b Null) = printf "if (%s) %s"         (show a) (show b)
   show (If a b c   ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
   show (Return e   ) = printf "return %s;" (show e)

src/Language/SystemVerilog/Parser/Lex.x

@@ -63,28 +63,30 @@ tokens :-
   "casex"            { tok KW_casex        }
   "casez"            { tok KW_casez        }
   "default"          { tok KW_default      }
+  "do"               { tok KW_do           }
   "else"             { tok KW_else         }
   "end"              { tok KW_end          }
   "endcase"          { tok KW_endcase      }
-  "endmodule"        { tok KW_endmodule    }
   "endfunction"      { tok KW_endfunction  }
   "endgenerate"      { tok KW_endgenerate  }
   "endinterface"     { tok KW_endinterface }
+  "endmodule"        { tok KW_endmodule    }
   "enum"             { tok KW_enum         }
-  "function"         { tok KW_function     }
   "for"              { tok KW_for          }
+  "forever"          { tok KW_forever      }
+  "function"         { tok KW_function     }
   "generate"         { tok KW_generate     }
   "genvar"           { tok KW_genvar       }
   "if"               { tok KW_if           }
   "initial"          { tok KW_initial      }
   "inout"            { tok KW_inout        }
   "input"            { tok KW_input        }
-  "interface"        { tok KW_interface    }
   "integer"          { tok KW_integer      }
+  "interface"        { tok KW_interface    }
   "localparam"       { tok KW_localparam   }
   "logic"            { tok KW_logic        }
-  "module"           { tok KW_module       }
   "modport"          { tok KW_modport      }
+  "module"           { tok KW_module       }
   "negedge"          { tok KW_negedge      }
   "or"               { tok KW_or           }
   "output"           { tok KW_output       }
@@ -92,11 +94,13 @@ tokens :-
   "parameter"        { tok KW_parameter    }
   "posedge"          { tok KW_posedge      }
   "reg"              { tok KW_reg          }
+  "repeat"           { tok KW_repeat       }
   "return"           { tok KW_return       }
   "static"           { tok KW_static       }
   "struct"           { tok KW_struct       }
   "typedef"          { tok KW_typedef      }
   "unique"           { tok KW_unique       }
+  "while"            { tok KW_while        }
   "wire"             { tok KW_wire         }
 
   @simpleIdentifier  { tok Id_simple  }

src/Language/SystemVerilog/Parser/Parse.y

@@ -28,6 +28,7 @@ import Language.SystemVerilog.Parser.Tokens
 "casex"            { Token KW_casex        _ _ }
 "casez"            { Token KW_casez        _ _ }
 "default"          { Token KW_default      _ _ }
+"do"               { Token KW_do           _ _ }
 "else"             { Token KW_else         _ _ }
 "end"              { Token KW_end          _ _ }
 "endcase"          { Token KW_endcase      _ _ }
@@ -36,8 +37,9 @@ import Language.SystemVerilog.Parser.Tokens
 "endinterface"     { Token KW_endinterface _ _ }
 "endmodule"        { Token KW_endmodule    _ _ }
 "enum"             { Token KW_enum         _ _ }
-"function"         { Token KW_function     _ _ }
 "for"              { Token KW_for          _ _ }
+"forever"          { Token KW_forever      _ _ }
+"function"         { Token KW_function     _ _ }
 "generate"         { Token KW_generate     _ _ }
 "genvar"           { Token KW_genvar       _ _ }
 "if"               { Token KW_if           _ _ }
@@ -48,8 +50,8 @@ import Language.SystemVerilog.Parser.Tokens
 "interface"        { Token KW_interface    _ _ }
 "localparam"       { Token KW_localparam   _ _ }
 "logic"            { Token KW_logic        _ _ }
-"module"           { Token KW_module       _ _ }
 "modport"          { Token KW_modport      _ _ }
+"module"           { Token KW_module       _ _ }
 "negedge"          { Token KW_negedge      _ _ }
 "or"               { Token KW_or           _ _ }
 "output"           { Token KW_output       _ _ }
@@ -57,11 +59,13 @@ import Language.SystemVerilog.Parser.Tokens
 "parameter"        { Token KW_parameter    _ _ }
 "posedge"          { Token KW_posedge      _ _ }
 "reg"              { Token KW_reg          _ _ }
+"repeat"           { Token KW_repeat       _ _ }
 "return"           { Token KW_return       _ _ }
 "static"           { Token KW_static       _ _ }
 "struct"           { Token KW_struct       _ _ }
 "typedef"          { Token KW_typedef      _ _ }
 "unique"           { Token KW_unique       _ _ }
+"while"            { Token KW_while        _ _ }
 "wire"             { Token KW_wire         _ _ }
 
 simpleIdentifier   { Token Id_simple       _ _ }
@@ -408,6 +412,10 @@ StmtNonAsgn :: { Stmt }
   | TimingControl Stmt                         { Timing $1 $2 }
   | "return" Expr ";"                          { Return $2 }
   | Identifier "(" CallArgs ")" ";"            { Subroutine $1 $3 }
+  | "while"  "(" Expr ")" Stmt                 { While   $3 $5 }
+  | "repeat" "(" Expr ")" Stmt                 { RepeatL $3 $5 }
+  | "do"      Stmt "while" "(" Expr ")" ";"    { DoWhile $5 $2 }
+  | "forever" Stmt                             { Forever $2 }
 
 DeclsAndStmts :: { ([Decl], [Stmt]) }
   : DeclOrStmt DeclsAndStmts { combineDeclsAndStmts $1 $2 }