allow extraneous semicolons in generate blocks

4b3b09d2 · Zachary Snow · 88c401e8 · 4b3b09d2 · 4b3b09d2
Commit 4b3b09d2 authored Feb 08, 2020 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+1 -0

test/basic/for_decl.sv
+1 -0

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1227,6 +1227,7 @@ GenItemOrNull :: { GenItem }

 GenItems :: { [GenItem] }
  : {- empty -}      { [] }
+  | GenItems ";"     { $1 }
  | GenItems GenItem { $1 ++ [$2] }

 GenItem :: { GenItem }

--- a/test/basic/for_decl.sv
+++ b/test/basic/for_decl.sv
@@ -66,6 +66,7 @@ module top;

    logic [0:31] c;
    generate
+        ;
        for (genvar n = 0; n < 32; n = n + 1)
            assign c[n] = n & 1;
    endgenerate