Commit 49e4f787 by Zachary Snow

conversion for always_latch (resolves #54)

parent ec0eecb5
{- sv2v {- sv2v
- Author: Zachary Snow <zach@zachjs.com> - Author: Zachary Snow <zach@zachjs.com>
- -
- Conversion for `always_comb` and `always_ff` - Conversion for `always_latch`, `always_comb`, and `always_ff`
- -
- `always_latch` -> `always @*`
- `always_comb` -> `always @*` - `always_comb` -> `always @*`
- `always_ff` -> `always` - `always_ff` -> `always`
-} -}
...@@ -16,6 +17,8 @@ convert :: [AST] -> [AST] ...@@ -16,6 +17,8 @@ convert :: [AST] -> [AST]
convert = map $ traverseDescriptions $ traverseModuleItems replaceAlwaysKW convert = map $ traverseDescriptions $ traverseModuleItems replaceAlwaysKW
replaceAlwaysKW :: ModuleItem -> ModuleItem replaceAlwaysKW :: ModuleItem -> ModuleItem
replaceAlwaysKW (AlwaysC AlwaysLatch stmt) =
AlwaysC Always $ Timing (Event SenseStar) stmt
replaceAlwaysKW (AlwaysC AlwaysComb stmt) = replaceAlwaysKW (AlwaysC AlwaysComb stmt) =
AlwaysC Always $ Timing (Event SenseStar) stmt AlwaysC Always $ Timing (Event SenseStar) stmt
replaceAlwaysKW (AlwaysC AlwaysFF stmt) = replaceAlwaysKW (AlwaysC AlwaysFF stmt) =
......
module test(a, b, en);
output logic a;
input logic b;
input logic en;
always_latch begin
if (en) begin
a <= b;
end
end
endmodule
module test(a, b, en);
output reg a;
input wire b;
input wire en;
always @(*) begin
if (en) begin
a <= b;
end
end
endmodule
module top;
wire a;
reg b;
reg en;
initial begin
en = 1;
forever #1 en = ~en;
end
test m(.a, .b, .en);
initial begin
$monitor($time, a, b, en);
#1; b = 1;
#1; b = 0;
#1; b = 0;
#1; b = 1;
#1; b = 0;
$finish;
end
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment