support complex sizes in size casts (resolves #69)

src/Language/SystemVerilog/Parser/Parse.y

@@ -421,6 +421,7 @@ time               { Token Lit_time        _ _ }
 %left  "*" "/" "%"
 %left  "**"
 %right REDUCE_OP "!" "~" "++" "--"
+%left "'"
 %left  "(" ")" "[" "]" "." "::"
 
 %%
@@ -1140,13 +1141,10 @@ Expr :: { Expr }
   | "{" Expr Concat "}"         { Repeat $2 $3 }
   | Concat                      { Concat $1 }
   | Expr "?" Expr ":" Expr      { Mux $1 $3 $5 }
-  | CastingType "'" "(" Expr ")" { Cast (Left            $1) $4 }
-  | Number      "'" "(" Expr ")" { Cast (Right $ Number  $1) $4 }
-  | "(" Expr ")" "'""(" Expr ")" { Cast (Right           $2) $6 }
-  |                 Identifier  "'" "(" Expr ")" { Cast (Right $ Ident   $1   ) $4 }
-  | Identifier "::" Identifier  "'" "(" Expr ")" { Cast (Right $ PSIdent $1 $3) $6 }
   | Expr "." Identifier         { Dot $1 $3 }
   | "'" "{" PatternItems "}"    { Pattern $3 }
+  | CastingType "'" "(" Expr ")" { Cast (Left  $1) $4 }
+  | Expr        "'" "(" Expr ")" { Cast (Right $1) $4 }
   | "{" StreamOp StreamSize Concat "}" { Stream $2 $3           $4 }
   | "{" StreamOp            Concat "}" { Stream $2 (Number "1") $3 }
   | Expr "inside" "{" OpenRangeList "}" { Inside $1 $4 }

test/basic/size_cast.sv

 module top;
     localparam BW = 3;
     logic [2:0] test;
-    assign test = BW'(0);
-    initial #1 $display(test);
+    logic [3:0] foo;
+    logic [3:0] bar;
+
+    initial begin
+        test = BW'(0);
+        $display(test);
+        foo = 2'('1);
+        $display(foo);
+        bar = $bits(bar)'('1);
+        $display(bar);
+    end
 endmodule

test/basic/size_cast.v

 module top;
-    localparam BW = 3;
-    wire [2:0] test;
-    assign test = 0;
-    initial #1 $display(test);
+    reg [2:0] test;
+    reg [3:0] foo;
+    reg [3:0] bar;
+
+    initial begin
+        test = 0;
+        $display(test);
+        foo = 4'b0011;
+        $display(foo);
+        bar = 4'b1111;
+        $display(bar);
+    end
 endmodule