support for multi-line defines

Language/SystemVerilog/Parser/Preprocess.hs

@@ -48,7 +48,10 @@ preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file
   where
   pp :: Bool -> [Bool] -> [(String, String)] -> [String] -> [String]
   pp _ _ _ [] = []
-  pp on stack env (a : rest) = case words a of
+  pp on stack env (a : rest) =
+    if a /= "" && last a == '\\' && head a == '`'
+    then pp on stack env $ ((init a) ++ " " ++ (head rest)) : (tail rest)
+    else case words a of
       "`define" : name : value -> "" : pp on stack (if on then (name, ppLine env $ unwords value) : env else env) rest
       "`ifdef"  : name : _     -> "" : pp (on && (elem    name $ fst $ unzip env)) (on : stack) env rest
       "`ifndef" : name : _     -> "" : pp (on && (notElem name $ fst $ unzip env)) (on : stack) env rest