preserve else block association (resolved #56)

src/Language/SystemVerilog/AST/Stmt.hs

@@ -94,7 +94,7 @@ instance Show Stmt where
     show (Forever s  ) = printf "forever %s" (show s)
     show (Foreach x i s) = printf "foreach (%s [ %s ]) %s" x (commas $ map (maybe "" id) i) (show s)
     show (If u a b Null) = printf "%sif (%s)%s"         (maybe "" showPad u) (show a) (showBranch b)
-    show (If u a b c   ) = printf "%sif (%s)%s\nelse%s" (maybe "" showPad u) (show a) (showBranch b) (showElseBranch c)
+    show (If u a b c   ) = printf "%sif (%s)%s\nelse%s" (maybe "" showPad u) (show a) (showBlockedBranch b) (showElseBranch c)
     show (Return e   ) = printf "return %s;" (show e)
     show (Timing t s ) = printf "%s%s" (show t) (showShortBranch s)
     show (Trigger b x) = printf "->%s %s;" (if b then "" else ">") x
@@ -107,6 +107,23 @@ showBranch :: Stmt -> String
 showBranch (block @ Block{}) = ' ' : show block
 showBranch stmt = '\n' : (indent $ show stmt)
 
+showBlockedBranch :: Stmt -> String
+showBlockedBranch stmt =
+    showBranch $
+    if isControl
+        then Block Seq "" [] [stmt]
+        else stmt
+    where
+        isControl = case stmt of
+            If{} -> True
+            For{} -> True
+            While{} -> True
+            RepeatL{} -> True
+            DoWhile{} -> True
+            Forever{} -> True
+            Foreach{} -> True
+            _ -> False
+
 showElseBranch :: Stmt -> String
 showElseBranch (stmt @ If{}) = ' ' : show stmt
 showElseBranch stmt = showBranch stmt

test/basic/else_prec.sv

+module top;
+
+    integer i;
+
+    task t;
+        input a, b, c;
+        begin
+
+            $display("1 (%b, %b, %b)", a, b, c);
+            if (a) begin
+                if (b) begin
+                    $display("FOO");
+                end
+            end else begin
+                if (c) begin
+                    $display("BAR");
+                end
+            end
+
+            $display("2 (%b, %b, %b)", a, b, c);
+            if (a) begin
+                for (i = 0; i < 1; ++i)
+                if (b) begin
+                    $display("FOO");
+                end
+            end else begin
+                if (c) begin
+                    $display("BAR");
+                end
+            end
+
+        end
+    endtask
+
+    initial begin
+        t(0, 0, 0);
+        t(0, 0, 1);
+        t(0, 1, 0);
+        t(0, 1, 1);
+        t(1, 0, 0);
+        t(1, 0, 1);
+        t(1, 1, 0);
+        t(1, 1, 1);
+    end
+
+endmodule

test/basic/else_prec.v

+// Reference file is already plain Verilog
+`include "else_prec.sv"