added new cache_request test from hdl examples

test/relong/cache_request.sv

+`default_nettype none
+
+`define CACHE_SETS 8
+`define CACHE_BLOCK_SIZE 'd16
+
+`define WORD_POISON 32'hBADF00D
+`define CACHE_PHYSICAL_TAG_POISON 22'h277BAD
+
+typedef logic [5:0] CacheIndex_t;
+typedef logic [3:0] CacheBlockOffset_t;
+typedef logic [19:0] CacheVirtualTag_t;
+typedef logic [21:0] CachePhysicalTag_t;
+typedef logic [$clog2(`CACHE_SETS)-1:0] CacheSetNumber_t;
+typedef logic [31:0] Word_t;
+
+typedef enum {CACHE_READ, CACHE_WRITE, CACHE_DRAM_FILL} CacheRequestType_t;
+
+`define CACHE_REQUEST_WIDTH 104
+
+typedef struct packed {
+    CacheIndex_t             index      ;
+    CacheBlockOffset_t       blockOffset;
+    // This field is only valid if requestType is a write
+    CachePhysicalTag_t            tag        ;
+    Word_t                   writeData     ;
+    CacheRequestType_t       requestType;
+    logic                    isValid    ;
+    logic              [3:0] writeEnable;
+    // The user must ensure that this set is safe to write to using the memory
+    // locking system.
+    CacheSetNumber_t writeSet;
+} CacheRequest_t;
+
+module CacheHelper (
+    input logic [5:0] index,
+    input logic [3:0] offset,
+    output logic [`CACHE_REQUEST_WIDTH-1:0] flatRequest
+);
+
+    generate
+        if($bits(CacheRequest_t) != `CACHE_REQUEST_WIDTH)
+            BadTypeLayout foo();
+    endgenerate
+
+    function automatic CacheRequest_t readRequestManual(CacheIndex_t index, CacheBlockOffset_t offset);
+        return '{
+            index: index,
+            blockOffset: offset,
+            tag: `CACHE_PHYSICAL_TAG_POISON,
+            writeData: `WORD_POISON,
+            requestType: CACHE_READ,
+            isValid: 1'b1,
+            writeEnable: 4'b0,
+            // This is effectively 32-bits wide which is sufficient, but not technically correct. The "compiler" will truncate the bits to the width of 'writeSet'
+            writeSet: '0
+        };
+    endfunction
+
+    CacheRequest_t request;
+
+    assign request = readRequestManual(index, offset);
+
+    assign flatRequest = request;
+
+endmodule
\ No newline at end of file

test/relong/cache_request.v

+`default_nettype none
+
+`define CACHE_SETS 8
+`define CACHE_BLOCK_SIZE 'd16
+
+`define WORD_POISON 32'hBADF00D
+`define CACHE_PHYSICAL_TAG_POISON 22'h277BAD
+
+// typedef logic [5:0] CacheIndex_t;
+// typedef logic [3:0] CacheBlockOffset_t;
+// typedef logic [19:0] CacheVirtualTag_t;
+// typedef logic [21:0] CachePhysicalTag_t;
+// typedef logic [$clog2(`CACHE_SETS)-1:0] CacheSetNumber_t;
+
+`define CACHE_REQUEST_WIDTH 104
+
+// typedef struct packed {
+//     CacheIndex_t             index      ;
+//     CacheBlockOffset_t       blockOffset;
+//     // This field is only valid if requestType is a write
+//     CachePhysicalTag_t            tag        ;
+//     Word_t                   writeData     ;
+//     CacheRequestType_t       requestType;
+//     logic                    isValid    ;
+//     logic              [3:0] writeEnable;
+//     // The user must ensure that this set is safe to write to using the memory
+//     // locking system.
+//     CacheSetNumber_t writeSet;
+// } CacheRequest_t;
+
+module CacheHelper (
+    input wire [5:0] index,
+    input wire [3:0] offset,
+    output wire [`CACHE_REQUEST_WIDTH-1:0] flatRequest
+);
+    // CacheRequestType_t
+    parameter CACHE_READ = 32'd0;
+    parameter CACHE_WRITE = 32'd1;
+    parameter CACHE_DRAM_FILL = 32'd2;
+
+    function [`CACHE_REQUEST_WIDTH-1:0] readRequestManual(input [5:0] index, input [3:0] offset);
+    begin
+        readRequestManual[2:0] = 4'b0; // writeSet: 32-bit literal in SV truncated to 4 bits in Verilog
+        readRequestManual[6:3] = 4'b0; // writeEnable
+        readRequestManual[7] = 1'b1; // isValid
+        readRequestManual[39:8] = CACHE_READ; // requestType
+        readRequestManual[71:40] = `WORD_POISON; // writeData
+        readRequestManual[93:72] = `CACHE_PHYSICAL_TAG_POISON; // tag
+        readRequestManual[97:94] = offset; // blockOffset
+        readRequestManual[103:98] = index; // index
+
+    end
+    endfunction
+
+    wire [`CACHE_REQUEST_WIDTH-1:0] request;
+
+    assign request = readRequestManual(index, offset);
+
+    assign flatRequest = request;
+
+endmodule
\ No newline at end of file

test/relong/cache_request_tb.v

+`default_nettype none
+
+module top;
+
+    wire [5:0] index;
+    wire [3:0] offset;
+    wire [103:0] flatRequest;
+    reg [10:0] dataIn;
+
+    CacheHelper dut(
+        .index(index),
+        .offset(offset),
+        .flatRequest(flatRequest)
+    );
+
+    assign {index, offset} = dataIn[9:0];
+
+    initial begin
+        $monitor($time, " %h %h = %h", index, offset, flatRequest);
+        for (dataIn = 11'h0; dataIn <= 10'h3ff; dataIn = dataIn + 11'h1) begin
+            #10;
+            if (94'h277bad0badf00d0000000080 != flatRequest[93:0])
+                $error("Bad fixed values");
+            if (dataIn[9:0] != flatRequest[103:94])
+                $error("Bad index/offset");
+        end
+    end
+endmodule
+