translate input reg to input wire

CHANGELOG.md

@@ -30,6 +30,7 @@
 
 * Added error checking for unresolved typenames
 * Added constant folding for `||` and `&&`
+* `input reg` module ports are now converted to `input wire`
 
 ## v0.0.11
 

src/Convert/Logic.hs

@@ -168,8 +168,16 @@ rewriteDeclM locations (Variable d (IntegerVector TLogic sg rs) x a e) = do
             let t' = Implicit sg rs
             insertElem accesses t'
             return $ Net d TWire DefaultStrength t' x a e
-rewriteDeclM _ decl@(Variable _ t x _ _) =
-    insertElem x t >> return decl
+rewriteDeclM locations decl@(Variable d t x a e) = do
+    inProcedure <- withinProcedureM
+    case (d, t, inProcedure) of
+        -- Reinterpret `input reg` module ports as `input logic`. We still don't
+        -- treat `logic` and `reg` as the same keyword, as specifying `reg`
+        -- explicitly is typically expected to flow downstream.
+        (Input, IntegerVector TReg sg rs, False) ->
+            rewriteDeclM locations $ Variable Input t' x a e
+            where t' = IntegerVector TLogic sg rs
+        _ -> insertElem x t >> return decl
 rewriteDeclM _ (Net d n s (IntegerVector _ sg rs) x a e) =
     insertElem x t >> return (Net d n s t x a e)
     where t = Implicit sg rs

test/core/input_reg.sv

+module Example(
+    input reg inp,
+    output reg out
+);
+    assign out = ~inp;
+endmodule

test/core/input_reg.v

+module Example(
+    input wire inp,
+    output wire out
+);
+    assign out = ~inp;
+endmodule

test/core/input_reg_tb.v

+module top;
+    reg inp;
+    wire out;
+    Example e(inp, out);
+    initial
+        repeat(5) begin
+            #1 inp = 0;
+            #1 inp = 1;
+        end
+endmodule