paramtype conversion resolves dimension queries before substitution

src/Convert/ParamType.hs

@@ -219,13 +219,27 @@ exprToType _ = Nothing
 -- TODO: If a type parameter contains an expression, that expression should be
 -- substituted into the new module, or created as a new parameter.
 isSimpleType :: Type -> Bool
-isSimpleType (IntegerVector _ _ _) = True
-isSimpleType (IntegerAtom   _ _  ) = True
-isSimpleType (NonInteger    _    ) = True
-isSimpleType (Net           _ _ _) = True
-isSimpleType (Struct   _ fields _) = all (isSimpleType . fst) fields
-isSimpleType (Union    _ fields _) = all (isSimpleType . fst) fields
-isSimpleType _ = False
+isSimpleType typ =
+    (not $ typeHasQueries typ) &&
+    case typ of
+        IntegerVector{} -> True
+        IntegerAtom  {} -> True
+        NonInteger   {} -> True
+        Net          {} -> True
+        Struct   _ fields _ -> all (isSimpleType . fst) fields
+        Union    _ fields _ -> all (isSimpleType . fst) fields
+        _ -> False
+
+-- returns whether a type contains any dimension queries
+typeHasQueries :: Type -> Bool
+typeHasQueries =
+    not . null . execWriter . collectTypeExprsM
+    (collectNestedExprsM collectUnresolvedExprM)
+    where
+        collectUnresolvedExprM :: Expr -> Writer [Expr] ()
+        collectUnresolvedExprM (expr @ DimsFn{}) = tell [expr]
+        collectUnresolvedExprM (expr @ DimFn {}) = tell [expr]
+        collectUnresolvedExprM _ = return ()
 
 -- attempt to rewrite instantiations with type parameters
 convertModuleItemM :: Info -> ModuleItem -> Writer Instances ModuleItem

test/basic/paramtype_bits.sv

+module Module(out);
+    parameter type T = logic;
+    output T out;
+    assign out = '1;
+endmodule
+
+module top;
+    logic w;
+    logic [$bits(w)-1:0] b;
+
+    logic o0, o1;
+    logic [1:0] o2;
+    Module                          m0(o0);
+    Module #(logic[$bits(w)-1:0])   m1(o1);
+    Module #(logic[$bits(b)*2-1:0]) m2(o2);
+endmodule

test/basic/paramtype_bits.v

+module Module_Size1(out);
+    output wire out;
+    assign out = 1'b1;
+endmodule
+
+module Module_Size2(out);
+    output wire [1:0] out;
+    assign out = 2'b11;
+endmodule
+
+module top;
+    wire w;
+    wire [0:0] b;
+
+    wire o0, o1;
+    wire [1:0] o2;
+    Module_Size1 m0(o0);
+    Module_Size1 m1(o1);
+    Module_Size2 m2(o2);
+endmodule