additional interface conversion test coverage

src/Convert/Interface.hs

@@ -24,7 +24,7 @@ data PartInfo = PartInfo
     } deriving Eq
 type PartInfos = Map.Map Identifier PartInfo
 
-type ModportInstances = [(Identifier, (Identifier, Identifier))]
+type ModportInstances = [(Identifier, Identifier)]
 type ModportBinding = (Identifier, (Substitutions, Expr))
 type Substitutions = [(Expr, Expr)]
 
@@ -185,7 +185,7 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
                 bindingIsBundle = lookupElem modports (Dot expr "") /= Nothing
                 portIsBundle = null modportName
                 modportName = case lookup portName modportInstances of
-                    Just (_, x) -> x
+                    Just x -> x
                     Nothing -> error $ "can't deduce modport for interface "
                         ++ show expr ++ " bound to port " ++ portName
 
@@ -259,15 +259,15 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
                         Just info = maybeInfo
                 collectDecl _ = return ()
 
-        extractModportInfo :: Type -> Maybe (Identifier, Identifier)
-        extractModportInfo (InterfaceT "" Nothing []) = Just ("", "")
+        extractModportInfo :: Type -> Maybe Identifier
+        extractModportInfo (InterfaceT "" Nothing []) = Just ""
         extractModportInfo (InterfaceT interfaceName (Just modportName) []) =
             if isInterface interfaceName
-                then Just (interfaceName, modportName)
+                then Just modportName
                 else Nothing
         extractModportInfo (Alias interfaceName []) =
             if isInterface interfaceName
-                then Just (interfaceName, "")
+                then Just ""
                 else Nothing
         extractModportInfo _ = Nothing
 
@@ -285,9 +285,8 @@ impliedModport =
     execWriter . mapM (collectNestedModuleItemsM collectModportDecls)
     where
         collectModportDecls :: ModuleItem -> Writer [ModportDecl] ()
-        collectModportDecls (MIPackageItem (Decl (Variable d _ x _ _))) =
-            tell [(d', x, Ident x)]
-            where d' = if d == Local then Inout else d
+        collectModportDecls (MIPackageItem (Decl (Variable _ _ x _ _))) =
+            tell [(Inout, x, Ident x)]
         collectModportDecls _ = return ()
 
 -- convert an interface-bound module instantiation or an interface instantiation
@@ -379,10 +378,6 @@ inlineInstance ranges modportBindings items
             case lookup (LHSDot (LHSBit lhs Tag) field) lhsReplacements of
                 Just resolved -> replaceLHSArrTag elt resolved
                 Nothing -> LHSDot (replaceLHS $ LHSBit lhs elt) field
-        replaceLHS (LHSBit lhs elt) =
-            case lookup (LHSBit lhs Tag) lhsReplacements of
-                Just resolved -> replaceLHSArrTag elt resolved
-                Nothing -> LHSBit (replaceLHS lhs) elt
         replaceLHS lhs =
             case lookup lhs lhsReplacements of
                 Just lhs' -> lhs'
@@ -402,12 +397,10 @@ inlineInstance ranges modportBindings items
         tagExpr :: Bool -> Scopes Expr -> Expr -> Expr
         tagExpr substitute scopes expr =
             case lookupElem scopes expr of
-                Just (_, _, Nil) -> Dot expr "@"
-                Just ([_, _], replacements, expr') ->
-                    if substitute && Map.null replacements
+                Just (_, _, expr') ->
+                    if substitute && expr' /= Nil
                         then Dot expr' "@"
                         else Dot expr "@"
-                Just (_, _, _) -> Dot expr "@"
                 Nothing ->
                     traverseSinglyNestedExprs (tagExpr substitute scopes) expr
         replaceExpr :: Expr -> Expr

test/basic/interface_array_indirect.sv

+interface Interface;
+    integer x;
+endinterface
+
+module Single(intf);
+    Interface intf;
+    initial #1 $display("Single %0d", intf.x);
+endmodule
+
+module Group(intfs);
+    parameter WIDTH = 1;
+    Interface intfs [WIDTH];
+    initial $display("Group %0d", WIDTH);
+    for (genvar i = 0; i < WIDTH; ++i)
+        Single s(intfs[i]);
+endmodule
+
+module top;
+    Interface intfs[8]();
+    for (genvar i = 0; i < 8; ++i)
+        initial intfs[i].x = i ** 3;
+    Group #(.WIDTH(8)) g(intfs);
+endmodule

test/basic/interface_array_indirect.v

+module top;
+    initial $display("Group %0d", 8);
+    generate
+        genvar i;
+        for (i = 0; i < 8; i = i + 1)
+            initial #1 $display("Single %0d", i ** 3);
+    endgenerate
+endmodule

test/basic/interface_array_output.sv

+interface Interface(output out);
+    assign out = 1;
+endinterface
+
+module top;
+    logic x;
+    Interface intfs[1](x);
+    initial $display(x);
+endmodule

test/basic/interface_array_output.v

+module top;
+    wire x = 1;
+    initial $display(x);
+endmodule

test/basic/interface_array_single.sv

@@ -33,6 +33,13 @@ module ModuleN(intf);
     Interface intf;
     `SHADOW
     initial #1 $display("ModuleN got %0d", intf.x);
+
+    typedef struct packed {
+        logic a, b;
+    } Struct;
+    Struct [1:0] structs;
+    assign structs[1].a = structs[0].b;
+    assign structs[0].a = structs[1].b;
 endmodule
 
 module top;

test/basic/interface_type_param.sv

+interface Interface;
+    parameter type T = logic [2:0];
+    initial $display($bits(T));
+endinterface
+
+module top;
+    Interface #(logic) a();
+    Interface #(byte) b();
+    Interface c();
+endmodule

test/basic/interface_type_param.v

+module top;
+    initial $display(1);
+    initial $display(8);
+    initial $display(3);
+endmodule

test/basic/interface_unbound.sv

+interface Interface(input x);
+    initial $display("Hello!");
+endinterface
+
+module Module(i);
+    Interface i;
+    initial #1 $display(i.x);
+endmodule
+
+module top;
+    Interface i1();
+    Module m1(i1);
+    Interface i2(.x());
+    Module m2(i2);
+endmodule

test/basic/interface_unbound.v

+module Module(x);
+    input wire x;
+    initial $display("Hello!");
+    initial #1 $display(x);
+endmodule
+
+module top;
+    generate
+        if (1) begin
+            wire x;
+            Module m1(x);
+            Module m2(x);
+        end
+    endgenerate
+endmodule

test/error/interface_excess_ports.sv

+interface Interface(input a, output b);
+    assign b = a;
+endinterface
+
+module top;
+    logic a, b, c;
+    Interface intf(a, b, c);
+endmodule

test/error/interface_missing_direction.sv

+interface Interface(a, b);
+    input a;
+    logic b;
+endinterface
+
+module top;
+    logic a, b;
+    Interface intf(a, b);
+endmodule

test/error/interface_modport_missing.sv

+interface Interface;
+    logic x;
+endinterface
+
+module Module(i, j);
+    Interface i;
+    logic j;
+    assign i.x = j.x;
+endmodule
+
+module top;
+    Interface i();
+    Interface j();
+    Module m(i, j);
+endmodule

test/error/interface_modport_unlisted.sv

+interface Interface;
+    logic x;
+endinterface
+
+module Module;
+    Interface i;
+endmodule

test/error/interface_non_lhs.sv

+interface Interface(input a, output b);
+    assign b = a;
+endinterface
+
+module top;
+    logic a, b;
+    Interface intf(a, b + 1);
+endmodule

test/error/interface_param_mismatch_expr.sv

+interface Interface;
+    parameter T = 0;
+    logic [T-1:0] x;
+endinterface
+
+module top;
+    Interface #(logic) intf();
+endmodule

test/error/interface_param_mismatch_type.sv

+interface Interface;
+    parameter type T;
+    T x;
+endinterface
+
+module top;
+    Interface #(1) intf();
+endmodule