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lvzhengyang
sv2v
Commits
219a57c3
Commit
219a57c3
authored
Jul 08, 2020
by
Zachary Snow
Browse files
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preliminary language support for parameterized class scopes
parent
296e2461
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Showing
13 changed files
with
100 additions
and
59 deletions
+100
-59
src/Convert/DimensionQuery.hs
+2
-2
src/Convert/Enum.hs
+1
-1
src/Convert/Interface.hs
+2
-2
src/Convert/NestPI.hs
+1
-1
src/Convert/Package.hs
+6
-4
src/Convert/ParamType.hs
+1
-2
src/Convert/Traverse.hs
+15
-1
src/Convert/Typedef.hs
+3
-3
src/Language/SystemVerilog/AST/Expr.hs
+24
-2
src/Language/SystemVerilog/AST/ModuleItem.hs
+2
-13
src/Language/SystemVerilog/AST/Type.hs
+14
-3
src/Language/SystemVerilog/Parser/Parse.y
+19
-17
src/Language/SystemVerilog/Parser/ParseDecl.hs
+10
-8
No files found.
src/Convert/DimensionQuery.hs
View file @
219a57c3
...
...
@@ -65,7 +65,7 @@ convertExpr (orig @ (DimsFn FnUnpackedDimensions (Left t))) =
convertExpr
(
orig
@
(
DimsFn
FnDimensions
(
Left
t
)))
=
case
t
of
IntegerAtom
{}
->
Number
"1"
Alias
{}
->
orig
CS
Alias
{}
->
orig
TypeOf
{}
->
orig
UnpackedType
t'
rs
->
BinOp
Add
...
...
@@ -95,7 +95,7 @@ convertExpr (DimFn f (Left t) (Number str)) =
Just
d
=
dm
r
=
rs
!!
(
fromIntegral
$
d
-
1
)
isUnresolved
::
Type
->
Bool
isUnresolved
(
Alias
{})
=
True
isUnresolved
(
CS
Alias
{})
=
True
isUnresolved
(
TypeOf
{})
=
True
isUnresolved
_
=
False
convertExpr
(
DimFn
f
(
Left
t
)
d
)
=
...
...
src/Convert/Enum.hs
View file @
219a57c3
...
...
@@ -60,7 +60,7 @@ convertDescription' description =
-- replace, but write down, enum types
traverseType
::
Type
->
Writer
Enums
Type
traverseType
(
Enum
(
t
@
Alias
{})
v
rs
)
=
traverseType
(
Enum
(
t
@
CS
Alias
{})
v
rs
)
=
return
$
Enum
t
v
rs
-- not ready
traverseType
(
Enum
(
Implicit
sg
rl
)
v
rs
)
=
traverseType
$
Enum
t'
v
rs
...
...
src/Convert/Interface.hs
View file @
219a57c3
...
...
@@ -92,7 +92,7 @@ convertDescription interfaces modules (Part attrs extern Module lifetime name po
InterfaceT
interfaceName
(
Just
modportName
)
[]
->
when
(
Map
.
member
interfaceName
interfaces
)
$
writeModport
interfaceName
modportName
Alias
Nothing
interfaceName
[]
->
Alias
interfaceName
[]
->
when
(
Map
.
member
interfaceName
interfaces
)
$
writeModport
interfaceName
""
_
->
return
()
...
...
@@ -195,7 +195,7 @@ convertDescription interfaces modules (Part attrs extern Module lifetime name po
modportDecls
=
lookupModport
interfaceItems
modportName
modportName
=
case
portType
of
InterfaceT
_
(
Just
x
)
[]
->
x
Alias
Nothing
_
[]
->
""
Alias
_
[]
->
""
_
->
error
$
"can't deduce modport for interface "
++
interfaceName
++
" bound to port "
++
portName
++
" of module "
++
moduleName
...
...
src/Convert/NestPI.hs
View file @
219a57c3
...
...
@@ -94,7 +94,7 @@ collectIdentsM _ = return ()
-- writes down aliased typenames
collectTypenamesM
::
Type
->
Writer
Idents
()
collectTypenamesM
(
Alias
_
x
_
)
=
tell
$
Set
.
singleton
x
collectTypenamesM
(
CSAlias
_
_
x
_
)
=
tell
$
Set
.
singleton
x
collectTypenamesM
_
=
return
()
-- returns the "name" of a package item, if it has one
...
...
src/Convert/Package.hs
View file @
219a57c3
...
...
@@ -111,8 +111,8 @@ prefixPackageItem packageName idents item =
Decl
(
ParamType
a
x
b
)
->
Decl
(
ParamType
a
(
prefix
x
)
b
)
other
->
other
convertTypeM
(
Alias
Nothing
x
rs
)
=
prefixM
x
>>=
\
x'
->
return
$
Alias
Nothing
x'
rs
convertTypeM
(
Alias
x
rs
)
=
prefixM
x
>>=
\
x'
->
return
$
Alias
x'
rs
convertTypeM
(
Enum
t
items
rs
)
=
mapM
prefixItem
items
>>=
\
items'
->
return
$
Enum
t
items'
rs
where
prefixItem
(
x
,
e
)
=
prefixM
x
>>=
\
x'
->
return
(
x'
,
e
)
...
...
@@ -201,12 +201,14 @@ traverseModuleItem _ _ item =
where
traverseExpr
::
Expr
->
Expr
traverseExpr
(
Ident
x
)
=
Ident
x
traverseExpr
(
PSIdent
x
y
)
=
Ident
$
x
++
"_"
++
y
traverseExpr
other
=
other
traverseType
::
Type
->
Type
traverseType
(
Alias
(
Just
ps
)
xx
rs
)
=
Alias
Nothing
(
ps
++
"_"
++
xx
)
rs
traverseType
(
Alias
xx
rs
)
=
Alias
xx
rs
traverseType
(
PSAlias
ps
xx
rs
)
=
Alias
(
ps
++
"_"
++
xx
)
rs
traverseType
other
=
other
-- returns the "name" of a package item, if it has one
...
...
src/Convert/ParamType.hs
View file @
219a57c3
...
...
@@ -199,8 +199,7 @@ defaultTag = "_sv2v_default"
-- attempt to convert an expression to syntactically equivalent type
exprToType
::
Expr
->
Maybe
Type
exprToType
(
Ident
x
)
=
Just
$
Alias
Nothing
x
[]
exprToType
(
PSIdent
x
y
)
=
Just
$
Alias
(
Just
x
)
y
[]
exprToType
(
CSIdent
x
p
y
)
=
Just
$
CSAlias
x
p
y
[]
exprToType
(
Range
e
NonIndexed
r
)
=
case
exprToType
e
of
Nothing
->
Nothing
...
...
src/Convert/Traverse.hs
View file @
219a57c3
...
...
@@ -431,6 +431,10 @@ traverseNestedExprsM mapper = exprMapper
em
(
Time
s
)
=
return
$
Time
s
em
(
Ident
i
)
=
return
$
Ident
i
em
(
PSIdent
x
y
)
=
return
$
PSIdent
x
y
em
(
CSIdent
x
ps
y
)
=
do
tes'
<-
mapM
typeOrExprMapper
$
map
snd
ps
let
ps'
=
zip
(
map
fst
ps
)
tes'
return
$
CSIdent
x
ps'
y
em
(
Range
e
m
(
e1
,
e2
))
=
do
e'
<-
exprMapper
e
e1'
<-
exprMapper
e1
...
...
@@ -517,8 +521,18 @@ exprMapperHelpers exprMapper =
b'
<-
exprMapper
b
return
(
a'
,
b'
)
typeOrExprMapper
(
Left
t
)
=
typeMapper
t
>>=
return
.
Left
typeOrExprMapper
(
Right
e
)
=
exprMapper
e
>>=
return
.
Right
typeMapper'
(
TypeOf
expr
)
=
exprMapper
expr
>>=
return
.
TypeOf
typeMapper'
(
CSAlias
x
pm
y
rs
)
=
do
vals'
<-
mapM
typeOrExprMapper
$
map
snd
pm
let
pm'
=
zip
(
map
fst
pm
)
vals'
rs'
<-
mapM
rangeMapper
rs
return
$
CSAlias
x
pm'
y
rs'
typeMapper'
t
=
do
let
(
tf
,
rs
)
=
typeRanges
t
rs'
<-
mapM
rangeMapper
rs
...
...
@@ -855,7 +869,7 @@ traverseNestedTypesM :: Monad m => MapperM m Type -> MapperM m Type
traverseNestedTypesM
mapper
=
fullMapper
where
fullMapper
=
mapper
>=>
tm
tm
(
Alias
ps
xx
rs
)
=
return
$
Alias
ps
xx
rs
tm
(
CSAlias
ps
pm
xx
rs
)
=
return
$
CSAlias
ps
pm
xx
rs
tm
(
Net
kw
sg
rs
)
=
return
$
Net
kw
sg
rs
tm
(
Implicit
sg
rs
)
=
return
$
Implicit
sg
rs
tm
(
IntegerVector
kw
sg
rs
)
=
return
$
IntegerVector
kw
sg
rs
...
...
src/Convert/Typedef.hs
View file @
219a57c3
...
...
@@ -79,10 +79,10 @@ traverseStmtM =
traverseExprTypesM
traverseTypeM
>=>
traverseExprM
traverseTypeM
::
Type
->
Scoper
Type
Type
traverseTypeM
(
Alias
Nothing
st
rs1
)
=
do
traverseTypeM
(
Alias
st
rs1
)
=
do
details
<-
lookupIdentM
st
return
$
case
details
of
Nothing
->
Alias
Nothing
st
rs1
Nothing
->
Alias
st
rs1
Just
(
_
,
_
,
typ
)
->
case
typ
of
Net
kw
sg
rs2
->
Net
kw
sg
$
rs1
++
rs2
Implicit
sg
rs2
->
Implicit
sg
$
rs1
++
rs2
...
...
@@ -91,7 +91,7 @@ traverseTypeM (Alias Nothing st rs1) = do
Struct
p
l
rs2
->
Struct
p
l
$
rs1
++
rs2
Union
p
l
rs2
->
Union
p
l
$
rs1
++
rs2
InterfaceT
x
my
rs2
->
InterfaceT
x
my
$
rs1
++
rs2
Alias
ps
x
rs2
->
Alias
ps
x
$
rs1
++
rs2
CSAlias
ps
pm
xx
rs2
->
CSAlias
ps
pm
x
x
$
rs1
++
rs2
UnpackedType
t
rs2
->
UnpackedType
t
$
rs1
++
rs2
IntegerAtom
kw
sg
->
nullRange
(
IntegerAtom
kw
sg
)
rs1
NonInteger
kw
->
nullRange
(
NonInteger
kw
)
rs1
...
...
src/Language/SystemVerilog/AST/Expr.hs
View file @
219a57c3
{-# LANGUAGE PatternSynonyms #-}
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
...
...
@@ -7,6 +8,8 @@
module
Language.SystemVerilog.AST.Expr
(
Expr
(
..
)
,
pattern
Ident
,
pattern
PSIdent
,
Range
,
TypeOrExpr
,
ExprOrRange
...
...
@@ -24,6 +27,8 @@ module Language.SystemVerilog.AST.Expr
,
endianCondRange
,
dimensionsSize
,
readNumber
,
ParamBinding
,
showParams
)
where
import
Data.Bits
(
shiftL
,
shiftR
)
...
...
@@ -45,8 +50,7 @@ data Expr
=
String
String
|
Number
String
|
Time
String
|
Ident
Identifier
|
PSIdent
Identifier
Identifier
|
CSIdent
Identifier
[
ParamBinding
]
Identifier
|
Range
Expr
PartSelectMode
Range
|
Bit
Expr
Expr
|
Repeat
Expr
[
Expr
]
...
...
@@ -66,12 +70,19 @@ data Expr
|
Nil
deriving
(
Eq
,
Ord
)
pattern
Ident
::
Identifier
->
Expr
pattern
Ident
x
=
PSIdent
""
x
pattern
PSIdent
::
Identifier
->
Identifier
->
Expr
pattern
PSIdent
x
y
=
CSIdent
x
[]
y
instance
Show
Expr
where
show
(
Nil
)
=
""
show
(
Number
str
)
=
str
show
(
Time
str
)
=
str
show
(
Ident
str
)
=
str
show
(
PSIdent
x
y
)
=
printf
"%s::%s"
x
y
show
(
CSIdent
x
p
y
)
=
printf
"%s#%s::%s"
x
(
showParams
p
)
y
show
(
String
str
)
=
printf
"
\"
%s
\"
"
str
show
(
Bit
e
b
)
=
printf
"%s[%s]"
(
show
e
)
(
show
b
)
show
(
Range
e
m
r
)
=
printf
"%s[%s%s%s]"
(
show
e
)
(
show
$
fst
r
)
(
show
m
)
(
show
$
snd
r
)
...
...
@@ -353,3 +364,14 @@ dimensionsSize ranges =
foldl
(
BinOp
Mul
)
(
Number
"1"
)
$
map
rangeSize
$
ranges
type
ParamBinding
=
(
Identifier
,
TypeOrExpr
)
showParams
::
[
ParamBinding
]
->
String
showParams
params
=
indentedParenList
$
map
showParam
params
showParam
::
ParamBinding
->
String
showParam
(
"*"
,
Right
Nil
)
=
".*"
showParam
(
i
,
arg
)
=
printf
fmt
i
(
either
show
show
arg
)
where
fmt
=
if
i
==
""
then
"%s%s"
else
".%s(%s)"
src/Language/SystemVerilog/AST/ModuleItem.hs
View file @
219a57c3
{-# LANGUAGE PatternSynonyms #-}
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
...
...
@@ -8,7 +9,6 @@
module
Language.SystemVerilog.AST.ModuleItem
(
ModuleItem
(
..
)
,
PortBinding
,
ParamBinding
,
ModportDecl
,
AlwaysKW
(
..
)
,
NInputGateKW
(
..
)
...
...
@@ -24,7 +24,7 @@ import Language.SystemVerilog.AST.ShowHelp
import
Language.SystemVerilog.AST.Attr
(
Attr
)
import
Language.SystemVerilog.AST.Decl
(
Direction
)
import
Language.SystemVerilog.AST.Description
(
PackageItem
)
import
Language.SystemVerilog.AST.Expr
(
Expr
(
Ident
,
Nil
),
Range
,
TypeOrExpr
,
showRange
s
)
import
Language.SystemVerilog.AST.Expr
(
Expr
(
Nil
),
pattern
Ident
,
Range
,
showRanges
,
ParamBinding
,
showParam
s
)
import
Language.SystemVerilog.AST.GenItem
(
GenItem
)
import
Language.SystemVerilog.AST.LHS
(
LHS
)
import
Language.SystemVerilog.AST.Stmt
(
Stmt
,
AssertionItem
,
Timing
(
Delay
))
...
...
@@ -89,15 +89,6 @@ showGate kw d x args =
delayStr
=
if
d
==
Nil
then
""
else
showPad
$
Delay
d
nameStr
=
showPad
$
Ident
x
showParams
::
[
ParamBinding
]
->
String
showParams
params
=
indentedParenList
$
map
showParam
params
showParam
::
ParamBinding
->
String
showParam
(
"*"
,
Right
Nil
)
=
".*"
showParam
(
i
,
arg
)
=
printf
fmt
i
(
either
show
show
arg
)
where
fmt
=
if
i
==
""
then
"%s%s"
else
".%s(%s)"
showModportDecl
::
ModportDecl
->
String
showModportDecl
(
dir
,
ident
,
t
,
e
)
=
if
e
==
Ident
ident
...
...
@@ -106,8 +97,6 @@ showModportDecl (dir, ident, t, e) =
type
PortBinding
=
(
Identifier
,
Expr
)
type
ParamBinding
=
(
Identifier
,
TypeOrExpr
)
type
ModportDecl
=
(
Direction
,
Identifier
,
Type
,
Expr
)
data
AlwaysKW
...
...
src/Language/SystemVerilog/AST/Type.hs
View file @
219a57c3
{-# LANGUAGE FlexibleInstances #-}
{-# LANGUAGE PatternSynonyms #-}
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
...
...
@@ -10,6 +11,8 @@ module Language.SystemVerilog.AST.Type
(
Identifier
,
Field
,
Type
(
..
)
,
pattern
Alias
,
pattern
PSAlias
,
Signing
(
..
)
,
Packing
(
..
)
,
NetType
(
..
)
...
...
@@ -42,7 +45,7 @@ data Type
|
NonInteger
NonIntegerType
|
Net
NetTypeAndStrength
Signing
[
Range
]
|
Implicit
Signing
[
Range
]
|
Alias
(
Maybe
Identifier
)
Identifier
[
Range
]
|
CSAlias
Identifier
[
ParamBinding
]
Identifier
[
Range
]
|
Enum
Type
[
Item
]
[
Range
]
|
Struct
Packing
[
Field
]
[
Range
]
|
Union
Packing
[
Field
]
[
Range
]
...
...
@@ -51,8 +54,16 @@ data Type
|
UnpackedType
Type
[
Range
]
-- used internally
deriving
(
Eq
,
Ord
)
pattern
Alias
::
Identifier
->
[
Range
]
->
Type
pattern
Alias
x
rs
=
PSAlias
""
x
rs
pattern
PSAlias
::
Identifier
->
Identifier
->
[
Range
]
->
Type
pattern
PSAlias
x
y
rs
=
CSAlias
x
[]
y
rs
instance
Show
Type
where
show
(
Alias
ps
xx
rs
)
=
printf
"%s%s%s"
(
maybe
""
(
++
"::"
)
ps
)
xx
(
showRanges
rs
)
show
(
Alias
xx
rs
)
=
printf
"%s%s"
xx
(
showRanges
rs
)
show
(
PSAlias
ps
xx
rs
)
=
printf
"%s::%s%s"
ps
xx
(
showRanges
rs
)
show
(
CSAlias
ps
pm
xx
rs
)
=
printf
"%s#%s::%s%s"
ps
(
showParams
pm
)
xx
(
showRanges
rs
)
show
(
Net
kw
sg
rs
)
=
printf
"%s%s%s"
(
show
kw
)
(
showPadBefore
sg
)
(
showRanges
rs
)
show
(
Implicit
sg
rs
)
=
printf
"%s%s"
(
showPad
sg
)
(
dropWhile
(
==
' '
)
$
showRanges
rs
)
show
(
IntegerVector
kw
sg
rs
)
=
printf
"%s%s%s"
(
show
kw
)
(
showPadBefore
sg
)
(
showRanges
rs
)
...
...
@@ -91,7 +102,7 @@ instance Ord (Signing -> [Range] -> Type) where
compare
tf1
tf2
=
compare
(
tf1
Unspecified
)
(
tf2
Unspecified
)
typeRanges
::
Type
->
([
Range
]
->
Type
,
[
Range
])
typeRanges
(
Alias
ps
xx
rs
)
=
(
Alias
ps
xx
,
rs
)
typeRanges
(
CSAlias
ps
pm
xx
rs
)
=
(
CSAlias
ps
pm
xx
,
rs
)
typeRanges
(
Net
kw
sg
rs
)
=
(
Net
kw
sg
,
rs
)
typeRanges
(
Implicit
sg
rs
)
=
(
Implicit
sg
,
rs
)
typeRanges
(
IntegerVector
kw
sg
rs
)
=
(
IntegerVector
kw
sg
,
rs
)
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
219a57c3
...
...
@@ -423,7 +423,7 @@ time { Token Lit_time _ _ }
%
left
"**"
%
right
REDUCE_OP
"!"
"~"
"++"
"--"
%
left
"'"
%
left
"("
")"
"["
"]"
"."
"::"
%
left
"("
")"
"["
"]"
"."
"::"
"#"
%%
...
...
@@ -444,8 +444,11 @@ Description :: { [Description] }
Type
::
{
Type
}
:
TypeNonIdent
{
$
1
}
|
Identifier
Dimensions
{
Alias
(
Nothing
)
$
1
$
2
}
|
Identifier
"::"
Identifier
Dimensions
{
Alias
(
Just
$
1
)
$
3
$
4
}
|
TypeAlias
{
$
1
}
TypeAlias
::
{
Type
}
:
Identifier
Dimensions
{
Alias
$
1
$
2
}
|
Identifier
"::"
Identifier
Dimensions
{
PSAlias
$
1
$
3
$
4
}
|
Identifier
ParamBindings
"::"
Identifier
Dimensions
{
CSAlias
$
1
$
2
$
4
$
5
}
TypeNonIdent
::
{
Type
}
:
PartialType
OptSigning
Dimensions
{
$
1
$
2
$
3
}
|
"type"
"("
Expr
")"
{
TypeOf
$
3
}
...
...
@@ -626,12 +629,13 @@ DeclToken :: { DeclToken }
|
Signing
{
%
posInject
\
p
->
DTSigning
p
$
1
}
|
ExplicitLifetime
{
%
posInject
\
p
->
DTLifetime
p
$
1
}
|
"const"
PartialType
{
%
posInject
\
p
->
DTType
p
$
2
}
|
Identifier
"::"
Identifier
{
%
posInject
\
p
->
DTPSIdent
p
$
1
$
3
}
|
"{"
StreamOp
StreamSize
Concat
"}"
{
%
posInject
\
p
->
DTStream
p
$
2
$
3
(
map
toLHS
$
4
)
}
|
"{"
StreamOp
Concat
"}"
{
%
posInject
\
p
->
DTStream
p
$
2
(
Number
"1"
)
(
map
toLHS
$
3
)
}
|
opt
(
"var"
)
"type"
"("
Expr
")"
{
%
posInject
\
p
->
DTType
p
(
\
Unspecified
->
\
[]
->
TypeOf
$
4
)
}
|
"<="
opt
(
DelayOrEvent
)
Expr
{
%
posInject
\
p
->
DTAsgn
p
AsgnOpNonBlocking
$
2
$
3
}
|
IncOrDecOperator
{
%
posInject
\
p
->
DTAsgn
p
(
AsgnOp
$
1
)
Nothing
(
Number
"1"
)
}
|
Identifier
"::"
Identifier
{
%
posInject
\
p
->
DTCSIdent
p
$
1
[]
$
3
}
|
Identifier
ParamBindings
"::"
Identifier
{
%
posInject
\
p
->
DTCSIdent
p
$
1
$
2
$
4
}
DeclTokenAsgn
::
{
DeclToken
}
:
"="
opt
(
DelayOrEvent
)
Expr
{
%
posInject
\
p
->
DTAsgn
p
AsgnOpEq
$
2
$
3
}
|
AsgnBinOp
Expr
{
%
posInject
\
p
->
DTAsgn
p
$
1
Nothing
$
2
}
...
...
@@ -1053,9 +1057,8 @@ ModuleParameterDecl(delim) :: { [Decl] }
|
"type"
TypeAsgns
delim
{
map
(
uncurry
$
ParamType
Parameter
)
$
2
}
ParameterDecl
(
delim
)
::
{
[
Decl
]
}
:
ParameterDeclKW
DeclAsgns
delim
{
makeParamDecls
$
1
(
Implicit
Unspecified
[]
)
$
2
}
|
ParameterDeclKW
ParamType
DeclAsgns
delim
{
makeParamDecls
$
1
(
$
2
)
$
3
}
|
ParameterDeclKW
Identifier
Dimensions
DeclAsgns
delim
{
makeParamDecls
$
1
(
Alias
(
Nothing
)
$
2
$
3
)
$
4
}
|
ParameterDeclKW
Identifier
"::"
Identifier
Dimensions
DeclAsgns
delim
{
makeParamDecls
$
1
(
Alias
(
Just
$
2
)
$
4
$
5
)
$
6
}
|
ParameterDeclKW
ParamType
DeclAsgns
delim
{
makeParamDecls
$
1
$
2
$
3
}
|
ParameterDeclKW
TypeAlias
DeclAsgns
delim
{
makeParamDecls
$
1
$
2
$
3
}
|
ParameterDeclKW
"type"
TypeAsgns
delim
{
map
(
uncurry
$
ParamType
$
1
)
$
3
}
ParameterDeclKW
::
{
ParamScope
}
:
"parameter"
{
Parameter
}
...
...
@@ -1079,8 +1082,13 @@ DelayOrEvent :: { Timing }
:
DelayControl
{
Delay
$
1
}
|
EventControl
{
Event
$
1
}
DelayControl
::
{
Expr
}
:
"#"
DelayValue
{
$
2
}
:
"#"
Number
{
Number
$
2
}
|
"#"
Time
{
Time
$
2
}
|
"#"
"("
Expr
")"
{
$
3
}
|
"#"
"("
Expr
":"
Expr
":"
Expr
")"
{
MinTypMax
$
3
$
5
$
7
}
|
"#"
Identifier
{
Ident
$
2
}
|
"#"
Identifier
"::"
Identifier
{
PSIdent
$
2
$
4
}
|
"#"
Identifier
ParamBindings
"::"
Identifier
{
CSIdent
$
2
$
3
$
5
}
CycleDelay
::
{
Expr
}
:
"##"
Expr
{
$
2
}
EventControl
::
{
Sense
}
...
...
@@ -1100,13 +1108,6 @@ Sense :: { Sense }
|
"posedge"
"("
LHS
")"
{
SensePosedge
$
3
}
|
"negedge"
"("
LHS
")"
{
SenseNegedge
$
3
}
DelayValue
::
{
Expr
}
:
Number
{
Number
$
1
}
|
Time
{
Time
$
1
}
|
Identifier
{
Ident
$
1
}
|
Identifier
"::"
Identifier
{
PSIdent
$
1
$
3
}
|
"("
Expr
":"
Expr
":"
Expr
")"
{
MinTypMax
$
2
$
4
$
6
}
CaseKW
::
{
CaseKW
}
:
"case"
{
CaseN
}
|
"casex"
{
CaseX
}
...
...
@@ -1174,8 +1175,6 @@ Expr :: { Expr }
|
DimsFn
"("
TypeOrExpr
")"
{
DimsFn
$
1
$
3
}
|
DimFn
"("
TypeOrExpr
")"
{
DimFn
$
1
$
3
(
Number
"1"
)
}
|
DimFn
"("
TypeOrExpr
","
Expr
")"
{
DimFn
$
1
$
3
$
5
}
|
Identifier
{
Ident
$
1
}
|
Identifier
"::"
Identifier
{
PSIdent
$
1
$
3
}
|
Expr
PartSelect
{
Range
$
1
(
fst
$
2
)
(
snd
$
2
)
}
|
Expr
"["
Expr
"]"
{
Bit
$
1
$
3
}
|
"{"
Expr
Concat
"}"
{
Repeat
$
2
$
3
}
...
...
@@ -1189,6 +1188,9 @@ Expr :: { Expr }
|
"{"
StreamOp
Concat
"}"
{
Stream
$
2
(
Number
"1"
)
$
3
}
|
Expr
"inside"
"{"
OpenRangeList
"}"
{
Inside
$
1
$
4
}
|
"("
Expr
":"
Expr
":"
Expr
")"
{
MinTypMax
$
2
$
4
$
6
}
|
Identifier
%
prec
REDUCE_OP
{- defer -}
{
Ident
$
1
}
|
Identifier
"::"
Identifier
{
PSIdent
$
1
$
3
}
|
Identifier
ParamBindings
"::"
Identifier
{
CSIdent
$
1
$
2
$
4
}
-- binary expressions
|
Expr
"||"
Expr
{
BinOp
LogOr
$
1
$
3
}
|
Expr
"&&"
Expr
{
BinOp
LogAnd
$
1
$
3
}
...
...
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
219a57c3
{-# LANGUAGE PatternSynonyms #-}
{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
...
...
@@ -37,6 +38,7 @@
module
Language.SystemVerilog.Parser.ParseDecl
(
DeclToken
(
..
)
,
pattern
DTIdent
,
parseDTsAsPortDecls
,
parseDTsAsModuleItems
,
parseDTsAsDecls
...
...
@@ -56,8 +58,7 @@ data DeclToken
|
DTAutoDim
Position
|
DTAsgn
Position
AsgnOp
(
Maybe
Timing
)
Expr
|
DTRange
Position
(
PartSelectMode
,
Range
)
|
DTIdent
Position
Identifier
|
DTPSIdent
Position
Identifier
Identifier
|
DTCSIdent
Position
Identifier
[
ParamBinding
]
Identifier
|
DTDir
Position
Direction
|
DTType
Position
(
Signing
->
[
Range
]
->
Type
)
|
DTParams
Position
[
ParamBinding
]
...
...
@@ -70,6 +71,8 @@ data DeclToken
|
DTLifetime
Position
Lifetime
deriving
(
Show
,
Eq
)
pattern
DTIdent
::
Position
->
Identifier
->
DeclToken
pattern
DTIdent
p
x
=
DTCSIdent
p
""
[]
x
-- entrypoints besides `parseDTsAsDeclOrStmt` use this to disallow `DTAsgn` with
-- a non-blocking operator, binary assignment operator, or a timing control
...
...
@@ -224,8 +227,8 @@ parseDTsAsDecl tokens =
-- [PUBLIC]: parser for single block item declarations or assign or arg-less
-- subroutine call statements
parseDTsAsDeclOrStmt
::
[
DeclToken
]
->
([
Decl
],
[
Stmt
])
parseDTsAsDeclOrStmt
[
DT
Ident
pos
f
]
=
(
[]
,
[
traceStmt
pos
,
Subroutine
(
Ident
f
)
(
Args
[]
[]
)])
parseDTsAsDeclOrStmt
[
DTPSIdent
pos
p
f
]
=
(
[]
,
[
traceStmt
pos
,
Subroutine
(
PSIdent
p
f
)
(
Args
[]
[]
)])
parseDTsAsDeclOrStmt
[
DT
CSIdent
pos
ps
pm
f
]
=
(
[]
,
[
traceStmt
pos
,
Subroutine
(
CSIdent
ps
pm
f
)
(
Args
[]
[]
)])
parseDTsAsDeclOrStmt
(
DTAsgn
pos
(
AsgnOp
op
)
mt
e
:
tok
:
toks
)
=
parseDTsAsDeclOrStmt
$
(
tok
:
toks
)
++
[
DTAsgn
pos
(
AsgnOp
op
)
mt
e
]
parseDTsAsDeclOrStmt
tokens
=
...
...
@@ -403,10 +406,9 @@ takeType (DTIdent _ a : DTDot _ b : rest) = (InterfaceT a (Just b), rest)
takeType
(
DTType
_
tf
:
DTSigning
_
sg
:
rest
)
=
(
tf
sg
,
rest
)
takeType
(
DTType
_
tf
:
rest
)
=
(
tf
Unspecified
,
rest
)
takeType
(
DTSigning
_
sg
:
rest
)
=
(
Implicit
sg
,
rest
)
takeType
(
DTPSIdent
_
ps
tn
:
rest
)
=
(
Alias
(
Just
ps
)
tn
,
rest
)
takeType
(
DTIdent
pos
tn
:
rest
)
=
if
couldBeTypename
then
(
Alias
(
Nothing
)
tn
,
rest
)
then
(
Alias
tn
,
rest
)
else
(
Implicit
Unspecified
,
DTIdent
pos
tn
:
rest
)
where
couldBeTypename
=
...
...
@@ -417,6 +419,7 @@ takeType (DTIdent pos tn : rest) =
(
_
,
Nothing
)
->
True
-- if comma is first, then this ident is a declaration
(
Just
a
,
Just
b
)
->
a
<
b
takeType
(
DTCSIdent
_
ps
pm
tn
:
rest
)
=
(
CSAlias
ps
pm
tn
,
rest
)
takeType
rest
=
(
Implicit
Unspecified
,
rest
)
takeRanges
::
[
DeclToken
]
->
([
Range
],
[
DeclToken
])
...
...
@@ -476,8 +479,7 @@ tokPos (DTComma p) = p
tokPos
(
DTAutoDim
p
)
=
p
tokPos
(
DTAsgn
p
_
_
_
)
=
p
tokPos
(
DTRange
p
_
)
=
p
tokPos
(
DTIdent
p
_
)
=
p
tokPos
(
DTPSIdent
p
_
_
)
=
p
tokPos
(
DTCSIdent
p
_
_
_
)
=
p
tokPos
(
DTDir
p
_
)
=
p
tokPos
(
DTType
p
_
)
=
p
tokPos
(
DTParams
p
_
)
=
p
...
...
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