simplify mod 1 to 0

17b01b16 · Zachary Snow · 5345a72c · 17b01b16 · 17b01b16 · 17b01b16
Commit 17b01b16 authored Jul 26, 2021 by Zachary Snow
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src/Convert/ExprUtils.hs
+1 -0

test/core/stream_unit.sv
+6 -0

test/core/stream_unit.v
+5 -0

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--- a/src/Convert/ExprUtils.hs
+++ b/src/Convert/ExprUtils.hs
@@ -84,6 +84,7 @@ simplifyBinOp Mul (Dec 0) _ = toDec 0
 simplifyBinOp Mul (Dec 1) e = e
 simplifyBinOp Mul _ (Dec 0) = toDec 0
 simplifyBinOp Mul e (Dec 1) = e
+simplifyBinOp Mod _ (Dec 1) = toDec 0
 simplifyBinOp Add e1 (UniOp UniSub e2) = BinOp Sub e1 e2
 simplifyBinOp Add (UniOp UniSub e1) e2 = BinOp Sub e2 e1

--- a/test/core/stream_unit.sv
+++ b/test/core/stream_unit.sv
+module top;
+    parameter W = 8;
+    logic [W - 1:0] x, y;
+    assign y = {<<{x}};
+    initial x = 8'b1101_0100;
+endmodule
--- a/test/core/stream_unit.v
+++ b/test/core/stream_unit.v
+module top;
+    parameter W = 8;
+    reg [W - 1:0] x = 8'b1101_0100;
+    wire [W - 1:0] y = 8'b0010_1011;
+endmodule